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Date: Tue, 12 Feb 2019 03:02:32 -0800 From: Moritz Fischer <moritz.fischer@...us.com> To: Nava kishore Manne <nava.manne@...inx.com> Cc: Alan Tull <atull@...nel.org>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Michal Simek <michal.simek@...inx.com>, Rajan Vaja <rajanv@...inx.com>, Jolly Shah <jollys@...inx.com>, linux-fpga@...r.kernel.org, Devicetree List <devicetree@...r.kernel.org>, linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, kishore m <chinnikishore369@...il.com> Subject: Re: [PATCH v3 2/3] dt-bindings: fpga: Add bindings for ZynqMP fpga driver Hi Nava, a couple of nits inline. otherwise looks fine to me. On Sun, Feb 10, 2019 at 8:17 AM Nava kishore Manne <nava.manne@...inx.com> wrote: > > Add documentation to describe Xilinx ZynqMP fpga driver > bindings. > > Signed-off-by: Nava kishore Manne <nava.manne@...inx.com> > --- > Changes for v3: > -Created patches on top of 5.0-rc5. > No functional changes. > Changes for v2: > -Removed "----" separators. > Changes for v1: > -Created a Seperate(New) DT binding file as > suggested by Rob. > > Changes for RFC-V2: > -Moved pcap node as a child to firwmare > node as suggested by Rob. > > .../devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > > diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > new file mode 100644 > index 0000000..1f6f588 > --- /dev/null > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt > @@ -0,0 +1,13 @@ > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled > +using ZynqMP SoC firmware interface How about: Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager. > +For Bitstream configuration on ZynqMp Soc uses processor configuration > +port(PCAP) to configure the programmable logic(PL) through PS by using > +FW interface. ZynqMP or ZynqMp, let's stay consistent here. How about: The ZynqMP SoC uses the PCAP (Processor configuration Port) to configure the Programmable Logic (PL). The configuration uses the firmware interface. > + > +Required properties: > +- compatible: should contain "xlnx,zynqmp-pcap-fpga" > + > +Example: > + zynqmp_pcap: pcap { > + compatible = "xlnx,zynqmp-pcap-fpga"; > + }; > -- > 2.7.4 > Thanks, Moritz
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