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Message-Id: <20190214083145.15148-1-benjamin.gaignard@linaro.org>
Date:   Thu, 14 Feb 2019 09:31:43 +0100
From:   Benjamin Gaignard <benjamin.gaignard@...aro.org>
To:     linux@...linux.org.uk, arnd@...db.de, alexandre.torgue@...com
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-stm32@...md-mailman.stormreply.com,
        benjamin.gaignard@...aro.org
Subject: [PATCH v2 0/2] ARM errata 814220

Implement ARM errata 814220 for Cortex A7.

This patch has been wroten by Jason Liu years ago but never send upstream.
I have tried to contact the author on multiple email addresses but I haven't
found any valid one...
I have keep Jason's sign-off and just rebase the patch on to v5-rc6.

version 2:
- limite help lines to 80 columns.
- Add  Arnd Bergmann acks.
  
Benjamin Gaignard (2):
  ARM: errata 814220-B-Cache maintenance by set/way operations can
    execute out of order.
  ARM: stm32: select ARM errata 814220

 arch/arm/Kconfig            | 12 ++++++++++++
 arch/arm/mach-stm32/Kconfig |  1 +
 arch/arm/mm/cache-v7.S      |  3 +++
 3 files changed, 16 insertions(+)

-- 
2.15.0

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