linux-kernel - RE: [PATCH V5 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <DB3PR0402MB39163EE75B512102C5FE19E9F5670@DB3PR0402MB3916.eurprd04.prod.outlook.com>
Date:   Thu, 14 Feb 2019 09:47:21 +0000
From:   Anson Huang <anson.huang@....com>
To:     Viresh Kumar <viresh.kumar@...aro.org>
CC:     "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "sboyd@...nel.org" <sboyd@...nel.org>,
        Aisheng Dong <aisheng.dong@....com>,
        Daniel Baluta <daniel.baluta@....com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        dl-linux-imx <linux-imx@....com>
Subject: RE: [PATCH V5 1/2] arm64: dts: freescale: imx8qxp: add cpu opp table

Hi, Viresh

Best Regards!
Anson Huang

> -----Original Message-----
> From: Viresh Kumar [mailto:viresh.kumar@...aro.org]
> Sent: 2019年2月14日 16:34
> To: Anson Huang <anson.huang@....com>
> Cc: robh+dt@...nel.org; mark.rutland@....com; shawnguo@...nel.org;
> s.hauer@...gutronix.de; kernel@...gutronix.de; festevam@...il.com;
> mturquette@...libre.com; sboyd@...nel.org; Aisheng Dong
> <aisheng.dong@....com>; Daniel Baluta <daniel.baluta@....com>;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org; linux-clk@...r.kernel.org; dl-linux-imx <linux-
> imx@....com>
> Subject: Re: [PATCH V5 1/2] arm64: dts: freescale: imx8qxp: add cpu opp
> table
> 
> On 14-02-19, 08:02, Anson Huang wrote:
> > Add i.MX8QXP CPU opp table to support cpufreq.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@....com>
> > ---
> > Changes since V4:
> > 	- remove redundant clock-latency property in A35_0;
> > 	- add #cooling-cells for all A35 core.
> > ---
> >  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 27
> > +++++++++++++++++++++++++++
> >  1 file changed, 27 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > index 4021f25..fad1259 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -34,6 +34,9 @@
> >  			reg = <0x0 0x0>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A35_L2>;
> > +			clocks = <&clk IMX_A35_CLK>;
> 
> As I said in my previous email, mentioning clocks is important too for other
> CPUs.

Although all CPUs share same clock and opp table, but OK, I will add clock to
all CPUs.

Anson.
> 
> > +			operating-points-v2 = <&a35_0_opp_table>;
> > +			#cooling-cells = <2>;
> >  		};
> >
> >  		A35_1: cpu@1 {
> > @@ -42,6 +45,8 @@
> >  			reg = <0x0 0x1>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A35_L2>;
> > +			operating-points-v2 = <&a35_0_opp_table>;
> > +			#cooling-cells = <2>;
> >  		};
> >
> >  		A35_2: cpu@2 {
> > @@ -50,6 +55,8 @@
> >  			reg = <0x0 0x2>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A35_L2>;
> > +			operating-points-v2 = <&a35_0_opp_table>;
> > +			#cooling-cells = <2>;
> >  		};
> >
> >  		A35_3: cpu@3 {
> > @@ -58,6 +65,8 @@
> >  			reg = <0x0 0x3>;
> >  			enable-method = "psci";
> >  			next-level-cache = <&A35_L2>;
> > +			operating-points-v2 = <&a35_0_opp_table>;
> > +			#cooling-cells = <2>;
> >  		};
> >
> >  		A35_L2: l2-cache0 {
> > @@ -65,6 +74,24 @@
> >  		};
> >  	};
> >
> > +	a35_0_opp_table: opp-table {
> > +		compatible = "operating-points-v2";
> > +		opp-shared;
> > +
> > +		opp-900000000 {
> > +			opp-hz = /bits/ 64 <900000000>;
> > +			opp-microvolt = <1000000>;
> > +			clock-latency-ns = <150000>;
> > +		};
> > +
> > +		opp-1200000000 {
> > +			opp-hz = /bits/ 64 <1200000000>;
> > +			opp-microvolt = <1100000>;
> > +			clock-latency-ns = <150000>;
> > +			opp-suspend;
> > +		};
> > +	};
> > +
> >  	gic: interrupt-controller@...00000 {
> >  		compatible = "arm,gic-v3";
> >  		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> > --
> > 2.7.4
> 
> --
> viresh