linux-kernel - Re: [PATCH v2 01/14] dt-bindings: remoteproc: Add TI PRUSS bindings

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Message-ID: <5C658DD6.8080309@ti.com>
Date:   Thu, 14 Feb 2019 17:48:38 +0200
From:   Roger Quadros <rogerq@...com>
To:     Marc Zyngier <marc.zyngier@....com>, Suman Anna <s-anna@...com>,
        "Davis, Andrew" <afd@...com>, Lokesh Vutla <lokeshvutla@...com>
CC:     Linus Walleij <linus.walleij@...aro.org>,
        ext Tony Lindgren <tony@...mide.com>,
        Ohad Ben-Cohen <ohad@...ery.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        David Lechner <david@...hnology.com>,
        "Nori, Sekhar" <nsekhar@...com>, Tero Kristo <t-kristo@...com>,
        <nsaulnier@...com>, <jreeder@...com>,
        Murali Karicheri <m-karicheri2@...com>,
        <woods.technical@...il.com>,
        Linux-OMAP <linux-omap@...r.kernel.org>,
        <linux-remoteproc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        DTML <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 01/14] dt-bindings: remoteproc: Add TI PRUSS bindings

fixed DTML id.

On 14/02/19 17:44, Roger Quadros wrote:
> On 14/02/19 14:52, Marc Zyngier wrote:
>> On Thu, 14 Feb 2019 10:55:10 +0000,
>> Roger Quadros <rogerq@...com> wrote:
>>>
>>>
>>> On 14/02/19 10:37, Linus Walleij wrote:
>>>> On Thu, Feb 14, 2019 at 4:13 AM Suman Anna <s-anna@...com> wrote:
>>>>> [Me]
>>>>
>>>>>> To be able to use hierarchical interrupt domain in the kernel, the top
>>>>>> interrupt controller must use the hierarchical (v2) irqdomain, so
>>>>>> if this is anything else than the ARM GIC it will be an interesting
>>>>>> undertaking to handle this.
>>>>>
>>>>> These are interrupt lines coming towards the host processor running
>>>>> Linux and are directly connected to the ARM GIC. This INTC module is
>>>>> actually an PRUSS internal interrupt controller that can take in 64 (on
>>>>> most SoCs) external events/interrupt sources and multiplexing them
>>>>> through two layers of many-to-one events-to-intr channels &
>>>>> intr-channels-to-host interrupts. Couple of the host interrupts go to
>>>>> the PRU cores themselves while the remaining ones come out of the IP to
>>>>> connect to other GICs in the SoC.
>>>>
>>>> If the muxing is static (like set up once at probe) so that while
>>>> the system is running, there is one and one only event mapped to
>>>> the GIC from the component below it, then it is hierarchical.
>>>
>>> This is how it looks.
>>>
>>> [GIC]<---8---[INTC]<---64---[events from peripherals]
>>>
>>> The 8 interrupt lines from INTC to the GIC are 1:1 mapped and fixed
>>> per SoC.  The muxing between 64 inputs to INTC and its 8 outputs are
>>> programmable and might not necessarily be static per boot/probe as
>>> it depends on what firmware is loaded on the PRU.
>>
>> But the point is that at any given time, there are at most 8 out of 64
>> inputs that are used, right? You *never* end-up with two (or more) of
>> these "events" being multiplexed on a single output line.
>>
> 
> Since the INTC's internal logic allows assigning more than one event each outputs,
> at most all 64 events can be assigned to one output or distributed among the 8 outputs.
> 
>> If these assertions do hold, then your design is typical of a
>> hierarchy, for which we have countless examples in the tree (including
>> for some TI HW).
> 
> OK.
> Suman, Andrew, Lokesh, thoughts?
> 

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