linux-kernel - Re: [PATCH v2] x86/tsc: Allow quick PIT calibration despite interruptions

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Message-ID: <20190215103637.GA55294@gmail.com>
Date:   Fri, 15 Feb 2019 11:36:37 +0100
From:   Ingo Molnar <mingo@...nel.org>
To:     Jan H. Schönherr <jan@...nhrr.de>
Cc:     Borislav Petkov <bp@...en8.de>, Ingo Molnar <mingo@...hat.com>,
        Thomas Gleixner <tglx@...utronix.de>, x86@...nel.org,
        Paul Menzel <pmenzel@...gen.mpg.de>,
        Thomas Lendacky <Thomas.Lendacky@....com>,
        "H. Peter Anvin" <hpa@...or.com>, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] x86/tsc: Allow quick PIT calibration despite
 interruptions


* Jan H. Schönherr <jan@...nhrr.de> wrote:

> Some systems experience regular interruptions (60 Hz SMI?), that prevent
> the quick PIT calibration from succeeding: individual interruptions can be
> so long, that the PIT MSB is observed to decrement by 2 or 3 instead of 1.
> The existing code cannot recover from this.
> 
> The system in question is an AMD Ryzen Threadripper 2950X, microcode
> 0x800820b, on an ASRock Fatal1ty X399 Professional Gaming, BIOS P3.30.
> 
> Change the code to handle (almost) arbitrary interruptions, as long
> as they happen only once in a while and they do not take too long.
> Specifically, also cover an interruption during the very first reads.
> 
> Signed-off-by: Jan H. Schönherr <jan@...nhrr.de>
> ---
> 
> v2:
> - Dropped the other hacky patch for the time being.
> - Fixed the early exit check.
> - Hopefully fixed all inaccurate math in v1.
> - Extended comments.
> 
>  arch/x86/kernel/tsc.c | 91 +++++++++++++++++++++++++++----------------
>  1 file changed, 57 insertions(+), 34 deletions(-)

BTW., I tried this on my Ryzen system, and it appears to be working well:

old (without patch):

  [    0.000000] tsc: Fast TSC calibration failed
  [    0.032000] tsc: PIT calibration matches HPET. 2 loops
  [    0.032000] tsc: Detected 3599.655 MHz processor
  [    0.000014] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x33e30d9825f, max_idle_ns: 440795248078 ns
  [    0.160104] clocksource: Switched to clocksource tsc-early
  [    1.468132] tsc: Refined TSC clocksource calibration: 3599.927 MHz
  [    1.478418] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x33e40e9d0e7, max_idle_ns: 440795301696 ns
  [    1.483197] clocksource: Switched to clocksource tsc

new (with patch):

  [    0.000000] tsc: Fast TSC calibration using PIT
  [    0.000000] tsc: Detected 3599.857 MHz processor
  [    0.736649] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x33e3cc37f8b, max_idle_ns: 440795303609 ns
  [    0.896736] clocksource: Switched to clocksource tsc-early
  [    2.212732] tsc: Refined TSC clocksource calibration: 3599.931 MHz
  [    2.218368] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x33e4128ece2, max_idle_ns: 440795387864 ns
  [    2.261799] clocksource: Switched to clocksource tsc

Tested-by: Ingo Molnar <mingo@...nel.org>

(Note that in the old log the printk timestamps start later so they are 
no basis for boot time comparison.)

Thanks,

	Ingo