lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Mon, 18 Feb 2019 14:10:57 +0800 From: Erin Lo <erin.lo@...iatek.com> To: Linus Walleij <linus.walleij@...aro.org> CC: Matthias Brugger <matthias.bgg@...il.com>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Thomas Gleixner <tglx@...utronix.de>, Jason Cooper <jason@...edaemon.net>, Marc Zyngier <marc.zyngier@....com>, Greg Kroah-Hartman <gregkh@...uxfoundation.org>, Stephen Boyd <sboyd@...eaurora.org>, <devicetree@...r.kernel.org>, srv_heupstream <srv_heupstream@...iatek.com>, <linux-kernel@...r.kernel.org>, <linux-serial@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>, <linux-arm-kernel@...ts.infradead.org>, <yingjoe.chen@...iatek.com>, <mars.cheng@...iatek.com>, <eddie.huang@...iatek.com>, <linux-clk@...r.kernel.org>, Ben Ho <Ben.Ho@...iatek.com>, Seiya Wang <seiya.wang@...iatek.com>, Weiyi Lu <weiyi.lu@...iatek.com>, Zhiyong Tao <zhiyong.tao@...iatek.com>, Hsin-Hsiung Wang <hsin-hsiung.wang@...iatek.com> Subject: Re: [PATCH v7 4/6] arm64: dts: Add Mediatek SoC MT8183 and evaluation board dts and Makefile On Fri, 2019-02-15 at 14:02 +0800, Erin Lo wrote: > From: Ben Ho <Ben.Ho@...iatek.com> > > Add basic chip support for Mediatek 8183, include > uart node with correct uart clocks, pwrap device > > Add clock controller nodes, include topckgen, infracfg, > apmixedsys and subsystem. > > Signed-off-by: Ben Ho <Ben.Ho@...iatek.com> > Signed-off-by: Erin Lo <erin.lo@...iatek.com> > Signed-off-by: Seiya Wang <seiya.wang@...iatek.com> > Signed-off-by: Weiyi Lu <weiyi.lu@...iatek.com> > Signed-off-by: Zhiyong Tao <zhiyong.tao@...iatek.com> > Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@...iatek.com> > Signed-off-by: Eddie Huang <eddie.huang@...iatek.com> > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 31 +++ > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 336 ++++++++++++++++++++++++++++ > 3 files changed, 368 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183-evb.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8183.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index e8f952f..458bbc4 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-evb.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-evb.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > new file mode 100644 > index 0000000..9b52559 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts > @@ -0,0 +1,31 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho <ben.ho@...iatek.com> > + * Erin Lo <erin.lo@...iatek.com> > + */ > + > +/dts-v1/; > +#include "mt8183.dtsi" > + > +/ { > + model = "MediaTek MT8183 evaluation board"; > + compatible = "mediatek,mt8183-evb", "mediatek,mt8183"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + memory@...00000 { > + device_type = "memory"; > + reg = <0 0x40000000 0 0x80000000>; > + }; > + > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > new file mode 100644 > index 0000000..1bd1399 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -0,0 +1,336 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (c) 2018 MediaTek Inc. > + * Author: Ben Ho <ben.ho@...iatek.com> > + * Erin Lo <erin.lo@...iatek.com> > + */ > + > +#include <dt-bindings/clock/mt8183-clk.h> > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "mediatek,mt8183"; > + interrupt-parent = <&sysirq>; > + #address-cells = <2>; > + #size-cells = <2>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x000>; > + enable-method = "psci"; > + }; > + > + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x001>; > + enable-method = "psci"; > + }; > + > + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x002>; > + enable-method = "psci"; > + }; > + > + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53"; > + reg = <0x003>; > + enable-method = "psci"; > + }; > + > + cpu4: cpu@100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x100>; > + enable-method = "psci"; > + }; > + > + cpu5: cpu@101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x101>; > + enable-method = "psci"; > + }; > + > + cpu6: cpu@102 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x102>; > + enable-method = "psci"; > + }; > + > + cpu7: cpu@103 { > + device_type = "cpu"; > + compatible = "arm,cortex-a73"; > + reg = <0x103>; > + enable-method = "psci"; > + }; > + }; > + > + pmu-a53 { > + compatible = "arm,cortex-a53-pmu"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; > + }; > + > + pmu-a73 { > + compatible = "arm,cortex-a73-pmu"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + clk26m: oscillator { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <26000000>; > + clock-output-names = "clk26m"; > + }; > + > + timer { > + compatible = "arm,armv8-timer"; > + interrupt-parent = <&gic>; > + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, > + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + gic: interrupt-controller@...0000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <4>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + reg = <0 0x0c000000 0 0x40000>, /* GICD */ > + <0 0x0c100000 0 0x200000>, /* GICR */ > + <0 0x0c400000 0 0x2000>, /* GICC */ > + <0 0x0c410000 0 0x1000>, /* GICH */ > + <0 0x0c420000 0 0x2000>; /* GICV */ > + > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; > + ppi-partitions { > + ppi_cluster0: interrupt-partition-0 { > + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; > + }; > + ppi_cluster1: interrupt-partition-1 { > + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; > + }; > + }; > + }; > + > + mcucfg: syscon@...0000 { > + compatible = "mediatek,mt8183-mcucfg", "syscon"; > + reg = <0 0x0c530000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + sysirq: interrupt-controller@...0a80 { > + compatible = "mediatek,mt8183-sysirq", > + "mediatek,mt6577-sysirq"; > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupt-parent = <&gic>; > + reg = <0 0x0c530a80 0 0x50>; > + }; > + > + topckgen: syscon@...00000 { > + compatible = "mediatek,mt8183-topckgen", "syscon"; > + reg = <0 0x10000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + infracfg: syscon@...01000 { > + compatible = "mediatek,mt8183-infracfg", "syscon"; > + reg = <0 0x10001000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pio: pinctrl@...05000 { > + compatible = "mediatek,mt8183-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11e80000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11e90000 0 0x1000>, > + <0 0x11d30000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11c50000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "iocfg0", "iocfg1", "iocfg2", > + "iocfg3", "iocfg4", "iocfg5", > + "iocfg6", "iocfg7", "iocfg8", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 192>; > + interrupt-controller; > + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>; > + interrupt-parent = <&gic>; interrupt-parent should be sysirq not gic We will remove it in next version. Best Regards, Erin > + #interrupt-cells = <4>; > + }; > + > + apmixedsys: syscon@...0c000 { > + compatible = "mediatek,mt8183-apmixedsys", "syscon"; > + reg = <0 0x1000c000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + pwrap: pwrap@...0d000 { > + compatible = "mediatek,mt8183-pwrap"; > + reg = <0 0x1000d000 0 0x1000>; > + reg-names = "pwrap"; > + interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, > + <&infracfg CLK_INFRA_PMIC_AP>; > + clock-names = "spi", "wrap"; > + }; > + > + uart0: serial@...02000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11002000 0 0x1000>; > + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart1: serial@...03000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11003000 0 0x1000>; > + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + uart2: serial@...04000 { > + compatible = "mediatek,mt8183-uart", > + "mediatek,mt6577-uart"; > + reg = <0 0x11004000 0 0x1000>; > + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; > + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; > + clock-names = "baud", "bus"; > + status = "disabled"; > + }; > + > + audiosys: syscon@...20000 { > + compatible = "mediatek,mt8183-audiosys", "syscon"; > + reg = <0 0x11220000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mfgcfg: syscon@...00000 { > + compatible = "mediatek,mt8183-mfgcfg", "syscon"; > + reg = <0 0x13000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + mmsys: syscon@...00000 { > + compatible = "mediatek,mt8183-mmsys", "syscon"; > + reg = <0 0x14000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + imgsys: syscon@...20000 { > + compatible = "mediatek,mt8183-imgsys", "syscon"; > + reg = <0 0x15020000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vdecsys: syscon@...00000 { > + compatible = "mediatek,mt8183-vdecsys", "syscon"; > + reg = <0 0x16000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + vencsys: syscon@...00000 { > + compatible = "mediatek,mt8183-vencsys", "syscon"; > + reg = <0 0x17000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_conn: syscon@...00000 { > + compatible = "mediatek,mt8183-ipu_conn", "syscon"; > + reg = <0 0x19000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_adl: syscon@...10000 { > + compatible = "mediatek,mt8183-ipu_adl", "syscon"; > + reg = <0 0x19010000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core0: syscon@...80000 { > + compatible = "mediatek,mt8183-ipu_core0", "syscon"; > + reg = <0 0x19180000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + ipu_core1: syscon@...80000 { > + compatible = "mediatek,mt8183-ipu_core1", "syscon"; > + reg = <0 0x19280000 0 0x1000>; > + #clock-cells = <1>; > + }; > + > + camsys: syscon@...00000 { > + compatible = "mediatek,mt8183-camsys", "syscon"; > + reg = <0 0x1a000000 0 0x1000>; > + #clock-cells = <1>; > + }; > + }; > +};
Powered by blists - more mailing lists