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Date:   Mon, 18 Feb 2019 09:49:31 +0100
From:   Maxime Ripard <maxime.ripard@...tlin.com>
To:     Yangtao Li <tiny.windzz@...il.com>
Cc:     srinivas.kandagatla@...aro.org, robh+dt@...nel.org,
        mark.rutland@....com, wens@...e.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/5] nvmem: sunxi-sid: add support for H5's SID controller

On Sun, Feb 17, 2019 at 11:23:13AM -0500, Yangtao Li wrote:
> Add support for H5's SID controller.
> 
> Signed-off-by: Yangtao Li <tiny.windzz@...il.com>
> ---
>  drivers/nvmem/sunxi_sid.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
> index 570a2e354f30..036029e90921 100644
> --- a/drivers/nvmem/sunxi_sid.c
> +++ b/drivers/nvmem/sunxi_sid.c
> @@ -219,11 +219,17 @@ static const struct sunxi_sid_cfg sun50i_a64_cfg = {
>  	.size = 0x100,
>  };
>  
> +static const struct sunxi_sid_cfg sun50i_h5_cfg = {
> +	.value_offset = 0x200,
> +	.size = 0x100,
> +};

IIRC, there was an endianness issue on the newer SoCs, with the driver
converting the data from big endian to little endian, while it's
actually stored little endian in the SID.

Have you checked the SID content?

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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