| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Mon, 18 Feb 2019 17:46:42 +0800
From: Xiaowei Bao <xiaowei.bao@....com>
To: bhelgaas@...gle.com, Zhiqiang.Hou@....com, robh+dt@...nel.org,
mark.rutland@....com, shawnguo@...nel.org, leoyang.li@....com,
kishon@...com, lorenzo.pieralisi@....com,
gregkh@...uxfoundation.org, l.subrahmanya@...iveil.co.in,
arnd@...db.de, Minghuan.Lian@....com, linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Xiaowei Bao <xiaowei.bao@....com>
Subject: [PATCH 5/6] arm64: dts: freescale: lx2160a: add pcie EP mode DT nodes
The LX2160A PCIe EP mode node.
Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
---
depends on: http://patchwork.ozlabs.org/project/linux-pci/list/?series=88754
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 56 ++++++++++++++++++++++++
1 files changed, 56 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 3a64f6e..5fee592 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -923,6 +923,15 @@
status = "disabled";
};
+ pcie_ep@...0000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ status = "disabled";
+ };
+
pcie@...0000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -950,6 +959,15 @@
status = "disabled";
};
+ pcie_ep@...0000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ status = "disabled";
+ };
+
pcie@...0000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -977,6 +995,16 @@
status = "disabled";
};
+ pcie_ep@...0000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x90 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ max-functions = <2>;
+ status = "disabled";
+ };
+
pcie@...0000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
@@ -1004,6 +1032,15 @@
status = "disabled";
};
+ pcie_ep@...0000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03700000 0x0 0x00100000
+ 0x98 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ status = "disabled";
+ };
+
pcie@...0000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
@@ -1031,6 +1068,16 @@
status = "disabled";
};
+ pcie_ep@...0000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03800000 0x0 0x00100000
+ 0xa0 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ max-functions = <2>;
+ status = "disabled";
+ };
+
pcie@...0000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
@@ -1058,5 +1105,14 @@
status = "disabled";
};
+ pcie_ep@...0000 {
+ compatible = "fsl,lx2160a-pcie-ep";
+ reg = <0x00 0x03900000 0x0 0x00100000
+ 0xa8 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ob-windows = <256>;
+ status = "disabled";
+ };
+
};
};
--
1.7.1
Powered by blists - more mailing lists