linux-kernel - RE: [EXT] Re: [PATCH net-next 10/13] net: mvpp2: reset the XPCS while reconfiguring the serdes lanes

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Message-ID: <DM5PR18MB106791EDF70EB40CD48BF7D8B0630@DM5PR18MB1067.namprd18.prod.outlook.com>
Date:   Mon, 18 Feb 2019 11:33:30 +0000
From:   Stefan Chulski <stefanc@...vell.com>
To:     Russell King - ARM Linux admin <linux@...linux.org.uk>
CC:     Antoine Tenart <antoine.tenart@...tlin.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "thomas.petazzoni@...tlin.com" <thomas.petazzoni@...tlin.com>,
        "maxime.chevallier@...tlin.com" <maxime.chevallier@...tlin.com>,
        "gregory.clement@...tlin.com" <gregory.clement@...tlin.com>,
        "miquel.raynal@...tlin.com" <miquel.raynal@...tlin.com>,
        Nadav Haklai <nadavh@...vell.com>,
        Yan Markman <ymarkman@...vell.com>,
        "mw@...ihalf.com" <mw@...ihalf.com>
Subject: RE: [EXT] Re: [PATCH net-next 10/13] net: mvpp2: reset the XPCS while
 reconfiguring the serdes lanes



> -----Original Message-----
> From: Russell King - ARM Linux admin <linux@...linux.org.uk>
> Sent: Monday, February 18, 2019 1:28 PM
> To: Stefan Chulski <stefanc@...vell.com>
> Cc: Antoine Tenart <antoine.tenart@...tlin.com>; davem@...emloft.net;
> netdev@...r.kernel.org; linux-kernel@...r.kernel.org;
> thomas.petazzoni@...tlin.com; maxime.chevallier@...tlin.com;
> gregory.clement@...tlin.com; miquel.raynal@...tlin.com; Nadav Haklai
> <nadavh@...vell.com>; Yan Markman <ymarkman@...vell.com>;
> mw@...ihalf.com
> Subject: Re: [EXT] Re: [PATCH net-next 10/13] net: mvpp2: reset the XPCS
> while reconfiguring the serdes lanes
> 
> Hi Stefan,
> 
> On Mon, Feb 18, 2019 at 11:08:34AM +0000, Stefan Chulski wrote:
> > HW recommendation upon Serdes reconfiguration are the following:
> >
> > 1. Disable port(CTRL0_REG - in XLG/GMAC) 2. Put port in reset (both
> > XLG/GMAC) 3. For KR - put in reset MPCS (MAC control clock, RX SD
> > clock, TX SD clock), XPSC is RXAUI/XAUI clock domain 4. Power down
> > Serdes lane
> >
> > Do reconfiguration of Serdes.
> >
> > 5. Enable Serdes lane
> > 6. Disable MPCS reset for KR
> > 7. Disable port reset (both XLG/GMAC)
> > 8. Enable port  (both XLG/GMAC)
> 
> For clarity, presumably either the XLG or the GMAC should be released from
> reset and enabled at any one time depending on the configured mode, but
> never both together?

Yes.
Only one of them the XLG or the GMAC ,depending on the configured mode.

Best Regards.