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Message-ID: <AM5PR04MB3299AE3A36D909AC192810D5F57C0@AM5PR04MB3299.eurprd04.prod.outlook.com>
Date: Tue, 19 Feb 2019 06:57:39 +0000
From: Xiaowei Bao <xiaowei.bao@....com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC: "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
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Subject: RE: [PATCHv6 1/4] dt-bindings: add DT binding for the layerscape PCIe
controller with EP mode
-----Original Message-----
From: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
Sent: 2019年2月6日 2:03
To: Xiaowei Bao <xiaowei.bao@....com>
Cc: bhelgaas@...gle.com; robh+dt@...nel.org; mark.rutland@....com; shawnguo@...nel.org; Leo Li <leoyang.li@....com>; kishon@...com; arnd@...db.de; gregkh@...uxfoundation.org; M.h. Lian <minghuan.lian@....com>; Mingkai Hu <mingkai.hu@....com>; Roy Zang <roy.zang@....com>; kstewart@...uxfoundation.org; cyrille.pitchen@...e-electrons.com; pombredanne@...b.com; shawn.lin@...k-chips.com; linux-pci@...r.kernel.org; devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linuxppc-dev@...ts.ozlabs.org
Subject: Re: [PATCHv6 1/4] dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
On Tue, Jan 22, 2019 at 02:33:25PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape
> PCIe controller with EP mode.
>
> Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
> Reviewed-by: Minghuan Lian <minghuan.lian@....com>
> Reviewed-by: Zhiqiang Hou <zhiqiang.hou@....com>
> Reviewed-by: Rob Herring <robh+dt@...nel.org>
> ---
> v2:
> - Add the SoC specific compatibles.
> v3:
> - modify the commit message.
> v4:
> - no change.
> v5:
> - no change.
> v6:
> - no change.
>
> .../devicetree/bindings/pci/layerscape-pci.txt | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
Applied the series to pci/layerscape for v5.1, thanks.
[Xiaowei Bao] Hi Lorenzo, thank a lot.
Lorenzo
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 9b2b8d6..e20ceaa 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -13,6 +13,7 @@ information.
>
> Required properties:
> - compatible: should contain the platform identifier such as:
> + RC mode:
> "fsl,ls1021a-pcie"
> "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
> "fsl,ls2088a-pcie"
> @@ -20,6 +21,8 @@ Required properties:
> "fsl,ls1046a-pcie"
> "fsl,ls1043a-pcie"
> "fsl,ls1012a-pcie"
> + EP mode:
> + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
> - reg: base addresses and lengths of the PCIe controller register blocks.
> - interrupts: A list of interrupt outputs of the controller. Must contain an
> entry for each entry in the interrupt-names property.
> --
> 1.7.1
>
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