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Message-ID: <CAGb2v65p0G83BVODsxxnXmiSCwuuwPFtY2k2ZV1F5xoFKrJjWQ@mail.gmail.com>
Date: Tue, 19 Feb 2019 15:54:00 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Maxime Ripard <maxime.ripard@...tlin.com>
Cc: Philipp Rossak <embed3d@...il.com>,
Emmanuel Vadot <manu@...ouilliste.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Jonathan Cameron <jic23@...nel.org>,
Quentin Schulz <quentin.schulz@...tlin.com>,
Icenowy Zheng <icenowy@...c.io>, linux-iio@...r.kernel.org,
devicetree <devicetree@...r.kernel.org>,
linux-sunxi <linux-sunxi@...glegroups.com>,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>
Subject: Allwinner SID THS calibration data cell representation?
Sorry for resurrecting an old discussion, but since someone posted patches
for H5 and H6, I thought we should resolve this. I'm working on patches to
fix / replace the big-endian issue.
On Thu, Sep 6, 2018 at 7:51 PM Maxime Ripard <maxime.ripard@...tlin.com> wrote:
>
> On Thu, Sep 06, 2018 at 01:47:47PM +0200, Philipp Rossak wrote:
> > On 04.09.2018 18:46, Emmanuel Vadot wrote:
> > > > + /* Data cells */
> > > > + thermal_calibration: calib@234 {
> > > > + reg = <0x234 0x8>;
> > > > + };
> > > You are declaring 8 bytes of calibration data but to my knowledge it's
> > > only 2 bytes per sensor, so 2 bytes for H3.
> > > Am I missing something ?
> > >
> > > Thanks,
> >
> > Emmanuel you are right, it is 2 bytes per Sensor and should be 2 bytes for
> > H3, but the thermal calibration data field is on all chips 64 bit wide - so
> > 8 bytes. So I'm reading here the complete calibration data field.
>
> Having one cell per channel would make more sense I guess.
Would it? The 2 32-bit words directly map onto the registers 0x74 / 0x78 in
the THS. As far as the SID is concerned, their is just one consumer for this
data, the thermal sensor. How the thermal sensor uses that data is really not
its concern. And the thermal sensor is really just copying the data from the
e-fuses into its registers. Nothing more.
Furthermore, with the register access interface, the e-fuses are read/write
32 bits at a time. Seems to me it would make more sense to enforce a 32-bit
word size, so cells should be multiples of 32 bits.
Regards
ChenYu
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