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Message-ID: <1550570914-26391-4-git-send-email-claudiu.beznea@microchip.com>
Date:   Tue, 19 Feb 2019 10:09:00 +0000
From:   <Claudiu.Beznea@...rochip.com>
To:     <thierry.reding@...il.com>, <robh+dt@...nel.org>,
        <mark.rutland@....com>, <Nicolas.Ferre@...rochip.com>,
        <alexandre.belloni@...tlin.com>, <Ludovic.Desroches@...rochip.com>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-pwm@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <Claudiu.Beznea@...rochip.com>
Subject: [PATCH v2 3/4] pwm: atmel: add support for SAM9X60's PWM controller

From: Claudiu Beznea <claudiu.beznea@...rochip.com>

Add support for SAM9X60's PWM controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@...rochip.com>
---
 drivers/pwm/pwm-atmel.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index 647d063562db..229cedb02770 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -52,6 +52,8 @@
 
 /* Only the LSB 16 bits are significant. */
 #define PWM_MAXV1_PRD		0xFFFF
+/* All 32 bits are significant. */
+#define PWM_MAXV2_PRD		0xFFFFFFFF
 #define PRD_MAXV1_PRES		10
 
 struct atmel_pwm_registers {
@@ -311,6 +313,20 @@ static const struct atmel_pwm_data atmel_pwm_data_v2 = {
 	},
 };
 
+static const struct atmel_pwm_data atmel_pwm_data_v3 = {
+	.regs = {
+		.period		= PWMV1_CPRD,
+		.period_upd	= PWMV1_CUPD,
+		.duty		= PWMV1_CDTY,
+		.duty_upd	= PWMV1_CUPD,
+	},
+	.cfg = {
+		/* 32 bits to keep period and duty. */
+		.max_period	= PWM_MAXV2_PRD,
+		.max_pres	= PRD_MAXV1_PRES,
+	},
+};
+
 static const struct platform_device_id atmel_pwm_devtypes[] = {
 	{
 		.name = "at91sam9rl-pwm",
@@ -335,6 +351,9 @@ static const struct of_device_id atmel_pwm_dt_ids[] = {
 		.compatible = "atmel,sama5d2-pwm",
 		.data = &atmel_pwm_data_v2,
 	}, {
+		.compatible = "microchip,sam9x60-pwm",
+		.data = &atmel_pwm_data_v3,
+	}, {
 		/* sentinel */
 	},
 };
-- 
2.7.4

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