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Date:   Thu, 21 Feb 2019 12:43:58 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Abel Vesa <abel.vesa@....com>, Aisheng Dong <aisheng.dong@....com>,
        Anson Huang <anson.huang@....com>,
        Fabio Estevam <fabio.estevam@....com>,
        Fabio Estevam <festevam@...il.com>,
        Jacky Bai <ping.bai@....com>,
        Lucas Stach <l.stach@...gutronix.de>,
        Mike Turquette <mturquette@...libre.com>,
        Sascha Hauer <kernel@...gutronix.de>,
        Shawn Guo <shawnguo@...nel.org>
Cc:     dl-linux-imx <linux-imx@....com>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Abel Vesa <abel.vesa@....com>
Subject: Re: [RESEND] clk: imx: Refactor entire sccg pll clk

Quoting Abel Vesa (2019-02-18 01:24:33)
> Make the entire combination of plls to be one single clock. The parents used
> for bypasses are specified each as an index in the parents list.
> The determine_rate does a lookup throughout all the possible combinations
> for all the divs and returns the best possible 'setup' which in turn is used
> by set_rate later to set up all the divs and bypasses.
> 
> Signed-off-by: Abel Vesa <abel.vesa@....com>
> Tested-by: Lucas Stach <l.stach@...gutronix.de>
> Acked-by: Lucas Stach <l.stach@...gutronix.de>
> ---

Applied to clk-next

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