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Date:   Wed, 27 Feb 2019 17:20:56 +0100
From:   Alexandre Torgue <alexandre.torgue@...com>
To:     Benjamin Gaignard <benjamin.gaignard@...aro.org>,
        <linux@...linux.org.uk>, <arnd@...db.de>,
        Russell King - ARM Linux <linux@...linux.org.uk>
CC:     <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>
Subject: Re: [PATCH v2 0/2] ARM errata 814220


On 2/14/19 9:31 AM, Benjamin Gaignard wrote:
> Implement ARM errata 814220 for Cortex A7.
> 
> This patch has been wroten by Jason Liu years ago but never send upstream.
> I have tried to contact the author on multiple email addresses but I haven't
> found any valid one...
> I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
> 
> version 2:
> - limite help lines to 80 columns.
> - Add  Arnd Bergmann acks.
>    
> Benjamin Gaignard (2):
>    ARM: errata 814220-B-Cache maintenance by set/way operations can
>      execute out of order.
>    ARM: stm32: select ARM errata 814220
> 
>   arch/arm/Kconfig            | 12 ++++++++++++
>   arch/arm/mach-stm32/Kconfig |  1 +
>   arch/arm/mm/cache-v7.S      |  3 +++
>   3 files changed, 16 insertions(+)
> 

Russel,

If you agree, can I take this series in my STM32 soc tree ?
If yes it will be part of my PR for v5.2.

regards
Alex

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