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Message-ID: <20190228142030.GB29231@dragon>
Date: Thu, 28 Feb 2019 22:20:32 +0800
From: Shawn Guo <shawnguo@...nel.org>
To: Abel Vesa <abel.vesa@....com>
Cc: Rob Herring <robh@...nel.org>, Mark Rutland <mark.rutland@....com>,
Sascha Hauer <kernel@...gutronix.de>,
Lucas Stach <l.stach@...gutronix.de>,
Angus Ainslie <angus.ainslie@...i.sm>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
Anson Huang <anson.huang@....com>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
dl-linux-imx <linux-imx@....com>,
Fabio Estevam <fabio.estevam@....com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 3/3] arm64: dts: imx8mq: Add the opp table and cores
opp properties
On Fri, Feb 15, 2019 at 06:07:24PM +0000, Abel Vesa wrote:
> Add the 0.8GHz and 1GHz opps. According to the datasheet:
> https://www.nxp.com/docs/en/data-sheet/IMX8MDQLQIEC.pdf
> section 3.1.3 Operating ranges.
>
> The 0.8GHz opp runs in nominal mode with the regulator set to 0.9V.
> The 1GHz runs in overdrive mode with the regulator set to 1V.
>
> Signed-off-by: Abel Vesa <abel.vesa@....com>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 23 +++++++++++++++++++++++
> 1 file changed, 23 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 1a89062..ebdec9e 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -91,6 +91,7 @@
> clocks = <&clk IMX8MQ_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + operating-points-v2 = <&a53_0_opp_table>;
> };
>
> A53_1: cpu@1 {
> @@ -101,6 +102,7 @@
> clocks = <&clk IMX8MQ_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + operating-points-v2 = <&a53_0_opp_table>;
> };
>
> A53_2: cpu@2 {
> @@ -111,6 +113,7 @@
> clocks = <&clk IMX8MQ_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + operating-points-v2 = <&a53_0_opp_table>;
> };
>
> A53_3: cpu@3 {
> @@ -121,6 +124,7 @@
> clocks = <&clk IMX8MQ_CLK_ARM>;
> enable-method = "psci";
> next-level-cache = <&A53_L2>;
> + operating-points-v2 = <&a53_0_opp_table>;
> };
>
> A53_L2: l2-cache0 {
> @@ -666,6 +670,25 @@
> status = "disabled";
> };
>
> +
> + a53_0_opp_table: opp-table {
What's the point of having '0' in the label name, considering it's
actually referred by all CPU nodes?
Shawn
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <900000>;
> + clock-latency-ns = <150000>;
> + };
> +
> + opp-1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <150000>;
> + opp-suspend;
> + };
> + };
> +
> gic: interrupt-controller@...00000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>, /* GIC Dist */
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@...ts.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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