lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Fri, 1 Mar 2019 10:18:37 +0100 From: Fabien Dessenne <fabien.dessenne@...com> To: Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Maxime Coquelin <mcoquelin.stm32@...il.com>, Alexandre Torgue <alexandre.torgue@...com>, <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <linux-stm32@...md-mailman.stormreply.com> CC: Fabien Dessenne <fabien.dessenne@...com> Subject: [PATCH 1/3] ARM: dts: stm32: add IPCC mailbox support on STM32MP157c Add configuration on DT for IPCC mailbox driver. Signed-off-by: Fabien Dessenne <fabien.dessenne@...com> --- arch/arm/boot/dts/stm32mp157c.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi index 10bf338..c664b55 100644 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@ -886,6 +886,21 @@ status = "disabled"; }; + ipcc: mailbox@...01000 { + compatible = "st,stm32mp1-ipcc"; + #mbox-cells = <1>; + reg = <0x4c001000 0x400>; + st,proc-id = <0>; + interrupts-extended = + <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <&exti 61 1>; + interrupt-names = "rx", "tx", "wakeup"; + clocks = <&rcc IPCC>; + wakeup-source; + status = "disabled"; + }; + rcc: rcc@...00000 { compatible = "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; -- 2.7.4
Powered by blists - more mailing lists