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Date:   Mon, 4 Mar 2019 18:55:50 +0000
From:   "Yu, Fenghua" <fenghua.yu@...el.com>
To:     "Hansen, Dave" <dave.hansen@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        H Peter Anvin <hpa@...or.com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        "Raj, Ashok" <ashok.raj@...el.com>,
        Peter Zijlstra <peterz@...radead.org>,
        "Shankar, Ravi V" <ravi.v.shankar@...el.com>,
        "Li, Xiaoyao" <xiaoyao.li@...el.com>
CC:     linux-kernel <linux-kernel@...r.kernel.org>, x86 <x86@...nel.org>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>
Subject: RE: [PATCH v4 05/17] x86/cpufeatures: Enumerate
 IA32_CORE_CAPABILITIES MSR

> From: Hansen, Dave
> On 3/1/19 6:44 PM, Fenghua Yu wrote:
> > diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> > index 6d6122524711..350eeccd0ce9 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -349,6 +349,7 @@
> >  #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single
> Thread Indirect Branch Predictors */
> >  #define X86_FEATURE_FLUSH_L1D		(18*32+28) /* Flush L1D
> cache */
> >  #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /*
> IA32_ARCH_CAPABILITIES MSR (Intel) */
> > +#define X86_FEATURE_CORE_CAPABILITY	(18*32+30) /*
> IA32_CORE_CAPABILITY MSR */
> >  #define X86_FEATURE_SPEC_CTRL_SSBD	(18*32+31) /* "" Speculative
> Store Bypass Disable */
> 
> What does this feature end up looking like in /proc/cpuinfo?

The flag string is "core_capability" in /proc/cpuinfo.

Thanks.

-Fenghua

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