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Date:   Tue, 5 Mar 2019 12:24:04 +0100
From:   Arnd Bergmann <>
To:     Marek Behún <>
Cc:     Linus Walleij <>,
        Tony Lindgren <>,
        Shawn Guo <>,
        "open list:GPIO SUBSYSTEM" <>,
        Linux Kernel Mailing List <>
Subject: Re: [PATCH v3 bus+gpio 1/5] bus: Add support for Moxtet bus

On Fri, Mar 1, 2019 at 5:02 AM Marek Behún <> wrote:
> On the Turris Mox router different modules can be connected to the main
> CPU board: currently a module with a SFP cage, a module with MiniPCIe
> connector, a 4-port switch module, an 8-port switch module, and a 4-port
> USB3 module.
> For example:
>   [CPU]-[PCIe]-[8-port switch]-[8-port switch]-[SFP]
> Each of this modules has an input and output shift register, and these
> are connected via SPI to the CPU board.
> Via SPI we are able to discover which modules are connected, in which
> order, and we can also read some information about the modules or
> configure them.
> From each module 8 bits can be read (of which low 4 bits identify the
> module) and 8 bits can be written.
> For example from the module with a SFP cage we can read the LOS,
> TX-FAULT and MOD-DEF0 signals, while we can write TX-DISABLE and
> RATE-SELECT signals.
> This driver creates a new bus type, called "moxtet". For each Mox module
> it finds via SPI, it creates a new device on the moxtet bus so that
> drivers can be written for them.
> The topology of how Mox modules are connected can then be read by
> listing /sys/bus/moxtet/devices.
> Signed-off-by: Marek Behún <>
> Acked-by: Linus Walleij <>

This looks very nice! I looked through the driver now and found nothing
to comment on other than the debugging properties that Linus already
mentioned, so please add my

Acked-by: Arnd Bergmann <>

and submit the next version to so we can pick it up
for linux-5.2.


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