lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Thu, 7 Mar 2019 11:02:25 -0800
From:   Sean Christopherson <sean.j.christopherson@...el.com>
To:     Vitaly Kuznetsov <vkuznets@...hat.com>
Cc:     Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        kvm@...r.kernel.org, Junaid Shahid <junaids@...gle.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 RFC] x86/kvm/mmu: make mmu->prev_roots cache work for
 NPT case

On Thu, Mar 07, 2019 at 10:59:46AM -0800, Sean Christopherson wrote:
> I think what we could do is repurpose role's nxe, cr0_wp, and
> sm{a,e}p_andnot_wp bits to uniquely identify a nested EPT/NPT entry.

Ignore the "NPT" comment, this would only apply to EPT.

> E.g. cr0_wp=1 and sm{a,e}p_andnot_wp=1 are an impossible combination.
> I'll throw together a patch to see what breaks.  In fact, I think we
> could revamp kvm_calc_shadow_ept_root_page_role() to completely ignore
> all legacy paging bits, i.e. handling changes in L2's configuration is
> L1's problem.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ