linux-kernel - RE: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field

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Date:   Tue, 12 Mar 2019 09:17:53 +0000
From:   "Z.q. Hou" <zhiqiang.hou@....com>
To:     Bjorn Helgaas <helgaas@...nel.org>
CC:     "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "l.subrahmanya@...iveil.co.in" <l.subrahmanya@...iveil.co.in>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Leo Li <leoyang.li@....com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will.deacon@....com" <will.deacon@....com>,
        Mingkai Hu <mingkai.hu@....com>,
        "M.h. Lian" <minghuan.lian@....com>,
        Xiaowei Bao <xiaowei.bao@....com>
Subject: RE: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field

Hi Bjorn,

Thanks a lot for your comments!

> -----Original Message-----
> From: Bjorn Helgaas [mailto:helgaas@...nel.org]
> Sent: 2019年3月11日 22:14
> To: Z.q. Hou <zhiqiang.hou@....com>
> Cc: linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> devicetree@...r.kernel.org; linux-kernel@...r.kernel.org;
> robh+dt@...nel.org; mark.rutland@....com; l.subrahmanya@...iveil.co.in;
> shawnguo@...nel.org; Leo Li <leoyang.li@....com>;
> lorenzo.pieralisi@....com; catalin.marinas@....com;
> will.deacon@....com; Mingkai Hu <mingkai.hu@....com>; M.h. Lian
> <minghuan.lian@....com>; Xiaowei Bao <xiaowei.bao@....com>
> Subject: Re: [PATCHv4 11/28] PCI: mobiveil: only fix up the Class Code field
> 
> On Mon, Mar 11, 2019 at 09:31:23AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@....com>
> >
> > Fix up the Class Code to PCI bridge, do not change the Revision ID.
> > And move the fixup to mobiveil_host_init function.
> 
> Add parens after function name.
> 
> Please explain why this change is needed.  Does it fix a bug?
> 
> Does this fix the problem that the PCI core didn't correctly identify the device
> as a bridge because it identified bridges by class code instead of header type?
> 
> That problem *should* be fixed by b2fb5cc57469 ("PCI: Rely on config space
> header type, not class code"), which is now upstream.
> 
> You might still want this class code change so that lspci shows the correct
> thing.  That's fine, but the changelog should say why we're doing it.
>

Subrahmanya's original patch is to fixup 'Class Code' field, but it also fixed the 'Revision ID' field. This patch is patch is to remove the fixup of 'Revision ID' field.

> > Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host Bridge IP
> > driver")
> 
> Make this "Fixes:" line a single line again.
> 
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> > Reviewed-by: Minghuan Lian <Minghuan.Lian@....com>
> > Reviewed-by: Subrahmanya Lingappa <l.subrahmanya@...iveil.co.in>
> > ---
> > V4:
> >  - no change
> >
> >  drivers/pci/controller/pcie-mobiveil.c | 9 ++++++---
> >  1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-mobiveil.c
> > b/drivers/pci/controller/pcie-mobiveil.c
> > index 78e575e71f4d..8eee1ab7ee24 100644
> > --- a/drivers/pci/controller/pcie-mobiveil.c
> > +++ b/drivers/pci/controller/pcie-mobiveil.c
> > @@ -653,6 +653,12 @@ static int mobiveil_host_init(struct mobiveil_pcie
> *pcie)
> >  				   type, resource_size(win->res));
> >  	}
> >
> > +	/* fixup for PCIe class register */
> > +	value = csr_readl(pcie, PAB_INTP_AXI_PIO_CLASS);
> > +	value &= 0xff;
> > +	value |= (PCI_CLASS_BRIDGE_PCI << 16);
> > +	csr_writel(pcie, value, PAB_INTP_AXI_PIO_CLASS);
> > +
> >  	/* setup MSI hardware registers */
> >  	mobiveil_pcie_enable_msi(pcie);
> >
> > @@ -896,9 +902,6 @@ static int mobiveil_pcie_probe(struct
> platform_device *pdev)
> >  		goto error;
> >  	}
> >
> > -	/* fixup for PCIe class register */
> > -	csr_writel(pcie, 0x060402ab, PAB_INTP_AXI_PIO_CLASS);
> > -
> >  	/* initialize the IRQ domains */
> >  	ret = mobiveil_pcie_init_irq_domain(pcie);
> >  	if (ret) {
> > --
> > 2.17.1
> >

Thanks,
Zhiqiang