linux-kernel - Re: [PATCHv2 1/5] Documentation: dt: edac: Fix Stratix10 IRQ bindings

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Message-ID: <CAL_JsqKnwYXSsP5B_uAaRoCEEV7Cb7f8XFPSC2z_hfSj7Rgqyg@mail.gmail.com>
Date:   Wed, 13 Mar 2019 14:23:53 -0500
From:   Rob Herring <robh@...nel.org>
To:     thor.thayer@...ux.intel.com
Cc:     Borislav Petkov <bp@...en8.de>, Dinh Nguyen <dinguyen@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        devicetree@...r.kernel.org, linux-edac@...r.kernel.org,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCHv2 1/5] Documentation: dt: edac: Fix Stratix10 IRQ bindings

On Tue, Mar 12, 2019 at 2:13 PM Thor Thayer <thor.thayer@...ux.intel.com> wrote:
>
> Hi Rob,
>
> On 3/12/19 11:00 AM, Rob Herring wrote:
> > On Wed, Feb 27, 2019 at 11:27:21AM -0600, thor.thayer@...ux.intel.com wrote:
> >> From: Thor Thayer <thor.thayer@...ux.intel.com>
> >>
> >> Fix Stratix10 ECC bindings to specify only the single
> >> bit error. On Stratix10 double bit errors are handled
> >> as SErrors instead of interrupts.
> >> Indicate the differences between the ARM64 and ARM32
> >> EDAC architecture in the bindings.
> >>
> >> Signed-off-by: Thor Thayer <thor.thayer@...ux.intel.com>
> >> ---
> >> v2 No change
> >> ---
> >>   .../devicetree/bindings/edac/socfpga-eccmgr.txt    | 23 +++++++++++++++-------
> >>   1 file changed, 16 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> >> index 5626560a6cfd..a0ac50e15912 100644
> >> --- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> >> +++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> >> @@ -236,33 +236,42 @@ Stratix10 SoCFPGA ECC Manager
> >>   The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
> >>   in a shared register similar to the Arria10. However, ECC requires
> >>   access to registers that can only be read from Secure Monitor with
> >> -SMC calls. Therefore the device tree is slightly different.
> >> +SMC calls. Therefore the device tree is slightly different. Note that
> >> +only 1 interrupt is sent because the double bit errors are treated as
> >> +SErrors instead of IRQ.
> >>
> >>   Required Properties:
> >>   - compatible : Should be "altr,socfpga-s10-ecc-manager"
> >> -- interrupts : Should be single bit error interrupt, then double bit error
> >> -    interrupt.
> >> +- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
> >> +                  containing the ECC manager registers.
> >
> > Seems this was already in use, but why not just make this node a child
> > of the System Manager Block and remove this phandle?
> >
> Yes, this was already in use but I'm trying to fix that oversight with
> this patch.
>
> The System Manager is a collection of registers used by different
> peripherals including EMAC and ECC.

The EMAC has its own registers too, right? But the ECC does not it seems.

> I view ECC Manager as a separate entity as is the Ethernet MAC which is
> why I have it separate. Using the phandle also follows the convention
> established with the Arria10 ECC Manager.

I guess this ship has sailed, so:

Acked-by: Rob Herring <robh@...nel.org>