lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Fri, 15 Mar 2019 08:35:31 +0000
From:   Anton Ivanov <anton.ivanov@...bridgegreys.com>
To:     Bartosz Golaszewski <brgl@...ev.pl>, Jeff Dike <jdike@...toit.com>,
        Richard Weinberger <richard@....at>,
        Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Bartosz Golaszewski <bgolaszewski@...libre.com>,
        linux-um@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] um: irq: don't set the chip for all irqs



On 14/03/2019 15:03, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bgolaszewski@...libre.com>
> 
> Setting a chip for an interrupt marks it as allocated. Since UM doesn't
> support dynamic interrupt numbers (yet), it means we cannot simply
> increase NR_IRQS and then use the free irqs between LAST_IRQ and NR_IRQS
> with gpio-mockup or iio testing drivers as irq_alloc_descs() will fail
> after not being able to neither find an unallocated range of interrupts
> nor expand the range.
> 
> Only call irq_set_chip_and_handler() for irqs until LAST_IRQ.
> 
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@...libre.com>
> ---
> Note: I plan to introduce support for SPARSE_IRQ but AFAICT it will be
> a bit more complicated, so in the meantime I'd like to propose this change.
> 
>   arch/um/kernel/irq.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c
> index f4874b7ec503..598d7b3d9355 100644
> --- a/arch/um/kernel/irq.c
> +++ b/arch/um/kernel/irq.c
> @@ -479,7 +479,7 @@ void __init init_IRQ(void)
>   	irq_set_chip_and_handler(TIMER_IRQ, &SIGVTALRM_irq_type, handle_edge_irq);
>   
>   
> -	for (i = 1; i < NR_IRQS; i++)
> +	for (i = 1; i < LAST_IRQ; i++)
>   		irq_set_chip_and_handler(i, &normal_irq_type, handle_edge_irq);
>   	/* Initialize EPOLL Loop */
>   	os_setup_epoll();
> 

Reviewed-by: Anton Ivanov <anton.ivanov@...bridgegreys.com>
Acked-by: Anton Ivanov <anton.ivanov@...bridgegreys.com>

-- 
Anton R. Ivanov
Cambridgegreys Limited. Registered in England. Company Number 10273661
https://www.cambridgegreys.com/

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ