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Message-ID: <20190315151241.GC48314@lakrids.cambridge.arm.com>
Date: Fri, 15 Mar 2019 15:12:41 +0000
From: Mark Rutland <mark.rutland@....com>
To: "Okamoto, Takayuki" <tokamoto@...fujitsu.com>
Cc: 'Will Deacon' <will.deacon@....com>,
'Catalin Marinas' <catalin.marinas@....com>,
'James Morse' <james.morse@....com>,
"'linux-kernel@...r.kernel.org'" <linux-kernel@...r.kernel.org>,
"'linux-arm-kernel@...ts.infradead.org'"
<linux-arm-kernel@...ts.infradead.org>,
"Zhang, Lei" <zhang.lei@...fujitsu.com>,
"hange-folder>?" <toggle-mailboxes@...rids.cambridge.arm.com>
Subject: Re: [RESEND PATCH] Make Fujitsu Erratum 010001 patch can be applied
on A64FX v1r0
On Fri, Mar 15, 2019 at 12:22:36PM +0000, Okamoto, Takayuki wrote:
> I resend the patch due to whitespace munging.
>
> > -----Original Message-----
> > From: James Morse <james.morse@....com>
> > Sent: Wednesday, February 27, 2019 3:44 AM
> > To: james.morse@....com; linux-arm-kernel@...ts.infradead.org
> > Cc: linux-kernel@...r.kernel.org; Catalin Marinas
> > <catalin.marinas@....com>; Mark Rutland <mark.rutland@....com>; Will
> > Deacon <will.deacon@....com>; Zhang, Lei <zhang.lei@...fujitsu.com>
> > Subject: [PATCH v5] arm64: Add workaround for Fujitsu A64FX erratum
> > 010001
> >
> > +/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> > +#define MIDR_FUJITSU_ERRATUM_010001
> > MIDR_FUJITSU_A64FX
> > +#define MIDR_FUJITSU_ERRATUM_010001_MASK
> > (~MIDR_VARIANT(1))
>
> This workaround for the erratum should be applied for both A64FX v1r0 and
> v0r0, however, the patch v5 is only enabled on A64FX v0r0(MIDR.Variant == 0
> && MIDR.Revision == 0).
> This issue is caused by the macro MIDR_FUJITSU_ERRATUM_010001_MASK.
>
> I have tested on both A64FX v1r0 and v0r0. This new patch will effect
> only for A64FX.
>
> --
> Changed to be applied for not only A64FX v0r0 but also v1r0.
>
> Signed-off-by: Zhang Lei <zhang.lei@...fujitsu.com>
> ---
> arch/arm64/include/asm/cputype.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
> index 2afb133..1fb47b5 100644
> --- a/arch/arm64/include/asm/cputype.h
> +++ b/arch/arm64/include/asm/cputype.h
> @@ -129,7 +129,7 @@
>
> /* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */
> #define MIDR_FUJITSU_ERRATUM_010001 MIDR_FUJITSU_A64FX
> -#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_VARIANT(1))
The bug is is that MIDR_VARIANT() is meant to extract the variant from a
full MIDR value, not generate an in-place field value.
> +#define MIDR_FUJITSU_ERRATUM_010001_MASK (~(0x1 << MIDR_VARIANT_SHIFT))
I beleive this can be:
#define MIDR_FUJITSU_ERRATUM_010001_MASK (~MIDR_VAR_REV(1, 0))
But otherwise this looks fine to me.
Thanks,
Mark.
> #define TCR_CLEAR_FUJITSU_ERRATUM_010001 (TCR_NFD1 | TCR_NFD0)
>
> #ifndef __ASSEMBLY__
> --
> 1.8.3.1
>
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