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Date:   Mon, 18 Mar 2019 18:35:32 +0200
From:   Stanimir Varbanov <svarbanov@...sol.com>
To:     Marc Gonzalez <marc.w.gonzalez@...e.fr>,
        Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>
Cc:     Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        PCI <linux-pci@...r.kernel.org>,
        MSM <linux-arm-msm@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Jeffrey Hugo <jhugo@...eaurora.org>
Subject: Re: [PATCH v3] PCI: qcom: Use default config space read function

Hi Marc,

Thanks for the patch!

On 3/18/19 4:28 PM, Marc Gonzalez wrote:
> We don't need to fudge the device class in qcom_pcie_rd_own_conf()
> because dw_pcie_setup_rc() already does the right thing:
> 
> 	/* Program correct class for RC */
> 	dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
> 
> However, the above has no effect on 8064, thus a fixup is required.
> 
> Signed-off-by: Marc Gonzalez <marc.w.gonzalez@...e.fr>
> ---
> Changes from v2 to v3: Add fixup for 8064 quirk
> Changes from v1 to v2: Completely drop qcom_pcie_rd_own_conf
> 
> Stanimir, could you test this submission and send a Tested-by if it works?
> ---
>  drivers/pci/controller/dwc/pcie-qcom.c | 23 ++++++-----------------
>  1 file changed, 6 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index d185ea5fe996..6fefff106b87 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -1129,25 +1129,8 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
>  	return ret;
>  }
>  
> -static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
> -				 u32 *val)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> -
> -	/* the device class is not reported correctly from the register */
> -	if (where == PCI_CLASS_REVISION && size == 4) {
> -		*val = readl(pci->dbi_base + PCI_CLASS_REVISION);
> -		*val &= 0xff;	/* keep revision id */
> -		*val |= PCI_CLASS_BRIDGE_PCI << 16;
> -		return PCIBIOS_SUCCESSFUL;
> -	}
> -
> -	return dw_pcie_read(pci->dbi_base + where, size, val);
> -}
> -
>  static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
>  	.host_init = qcom_pcie_host_init,
> -	.rd_own_conf = qcom_pcie_rd_own_conf,
>  };
>  
>  /* Qcom IP rev.: 2.1.0	Synopsys IP rev.: 4.01a */
> @@ -1299,6 +1282,12 @@ static int qcom_pcie_probe(struct platform_device *pdev)
>  	return ret;
>  }
>  
> +static void qcom_fixup_class(struct pci_dev *dev)
> +{
> +	dev->class = PCI_CLASS_BRIDGE_PCI << 8;
> +}
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); // 8064

Please make 0x101 a define, and drop //

I will try to find device IDs for ipq8064 and ipq4019.

-- 
regards,
Stan

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