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Message-ID: <20190319142756.GB2095@latitude>
Date: Tue, 19 Mar 2019 15:27:56 +0100
From: Jonathan Neuschäfer <j.neuschaefer@....net>
To: Aisheng Dong <aisheng.dong@....com>
Cc: Jonathan Neuschäfer <j.neuschaefer@....net>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
dl-linux-imx <linux-imx@....com>,
Lucas Stach <l.stach@...gutronix.de>,
Michael Grzeschik <m.grzeschik@...gutronix.de>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH RESEND] clk: imx5: Fix i.MX50 clock registers
On Tue, Mar 19, 2019 at 02:16:51PM +0000, Aisheng Dong wrote:
> > From: Jonathan Neuschäfer [mailto:j.neuschaefer@....net]
> >
> > There are a few differences between the i.MX50 clock tree and those of
> > i.MX51 and i.MX53 that are not yet handled in clk-imx51-imx53.c.
> > This patch handles the following differences:
> >
> > - i.MX50 does not have a periph_apm clock. Instead, the main bus clock
> > (a.k.a. periph_clk) comes directly from a MUX between pll1_sw,
> > pll2_sw, pll3_sw, and lp_apm.
> > - The MUX bits for esdhc_{a,c,d}_sel are shifted by one bit within
> > CSCMR1.
> >
>
> Can you please split them into two patches?
> Otherwise, the fix seems good to me.
Ok, I'll do that.
Jonathan Neuschäfer
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