linux-kernel - Re: [PATCH 05/22] perf/x86: Support constraint ranges

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20190319145309.GI5996@hirez.programming.kicks-ass.net>
Date:   Tue, 19 Mar 2019 15:53:09 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     kan.liang@...ux.intel.com
Cc:     acme@...nel.org, mingo@...hat.com, linux-kernel@...r.kernel.org,
        tglx@...utronix.de, jolsa@...nel.org, eranian@...gle.com,
        alexander.shishkin@...ux.intel.com, ak@...ux.intel.com
Subject: Re: [PATCH 05/22] perf/x86: Support constraint ranges

On Mon, Mar 18, 2019 at 02:41:27PM -0700, kan.liang@...ux.intel.com wrote:
> From: Andi Kleen <ak@...ux.intel.com>
> 
> Icelake extended the general counters to 8, even when SMT is enabled.
> However only a (large) subset of the events can be used on all 8
> counters.
> 
> The events that can or cannot be used on all counters are organized
> in ranges.
> 
> We need a lot of scheduler constraints to handle all this.
> 
> To avoid blowing up the tables add event code ranges to the constraint
> tables, and a new inline function to match them.
> 
> The changes costs ~2k text size according to 0day report.

Where?! there isn't much code here.

> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
> ---
>  arch/x86/events/intel/core.c |  2 +-
>  arch/x86/events/intel/ds.c   |  2 +-
>  arch/x86/events/perf_event.h | 34 ++++++++++++++++++++++++++++++++++
>  3 files changed, 36 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index a964b9832b0c..8486ab87f8f8 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2655,7 +2655,7 @@ x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
>  
>  	if (x86_pmu.event_constraints) {
>  		for_each_event_constraint(c, x86_pmu.event_constraints) {
> -			if ((event->hw.config & c->cmask) == c->code) {
> +			if (constraint_match(c, event->hw.config)) {
>  				event->hw.flags |= c->flags;
>  				return c;
>  			}
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index 974284c5ed6c..30370fb93e21 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -858,7 +858,7 @@ struct event_constraint *intel_pebs_constraints(struct perf_event *event)
>  
>  	if (x86_pmu.pebs_constraints) {
>  		for_each_event_constraint(c, x86_pmu.pebs_constraints) {
> -			if ((event->hw.config & c->cmask) == c->code) {
> +			if (constraint_match(c, event->hw.config)) {
>  				event->hw.flags |= c->flags;
>  				return c;
>  			}
> @@ -71,6 +72,12 @@ struct event_constraint {
>  #define PERF_X86_EVENT_AUTO_RELOAD	0x0400 /* use PEBS auto-reload */
>  #define PERF_X86_EVENT_LARGE_PEBS	0x0800 /* use large PEBS */
>  
> +static inline bool constraint_match(struct event_constraint *c, u64 ecode)
> +{
> +	ecode &= c->cmask;
> +	return ecode == c->code ||
> +		(c->range_end && ecode >= c->code && ecode <= c->range_end);
> +}
>  
>  struct amd_nb {
>  	int nb_id;  /* NorthBridge id */

That's all the code, how does that add up to 2k ?