lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20190320005958.GA18687@leoy-ThinkPad-X240s>
Date:   Wed, 20 Mar 2019 08:59:58 +0800
From:   Leo Yan <leo.yan@...aro.org>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        stable@...r.kernel.org, Zhong Kaihua <zhongkaihua@...wei.com>,
        John Stultz <john.stultz@...aro.org>,
        Zhangfei Gao <zhangfei.gao@...aro.org>
Subject: Re: [RESEND PATCH] clk: hi3660: Mark clk_gate_ufs_subsys as critical

On Tue, Mar 19, 2019 at 12:42:43PM -0700, Stephen Boyd wrote:
> Quoting Leo Yan (2019-03-19 02:31:48)
> > diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c
> > index f40419959656..32ba80181cc6 100644
> > --- a/drivers/clk/hisilicon/clk-hi3660.c
> > +++ b/drivers/clk/hisilicon/clk-hi3660.c
> > @@ -164,7 +164,7 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = {
> >         { HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2",
> >           "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
> >         { HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
> > -         CLK_SET_RATE_PARENT, 0x50, 21, 0, },
> > +         CLK_SET_RATE_PARENT|CLK_IS_CRITICAL, 0x50, 21, 0, },
> 
> Nitpick: Please add space around | and also comment in the code why this
> is a critical clk.

Will fix it and spin a new patch.

Thanks for suggestions, Stephen.

> >         { HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
> >           CLK_SET_RATE_PARENT, 0x50, 28, 0, },
> >         { HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ