linux-kernel - [PATCH v2] clk: hi3660: Mark clk_gate_ufs

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Message-Id: <20190320100508.6950-1-leo.yan@linaro.org>
Date:   Wed, 20 Mar 2019 18:05:08 +0800
From:   Leo Yan <leo.yan@...aro.org>
To:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org
Cc:     Leo Yan <leo.yan@...aro.org>, stable@...r.kernel.org,
        Zhong Kaihua <zhongkaihua@...wei.com>,
        John Stultz <john.stultz@...aro.org>,
        Zhangfei Gao <zhangfei.gao@...aro.org>
Subject: [PATCH v2] clk: hi3660: Mark clk_gate_ufs_subsys as critical

clk_gate_ufs_subsys is a system bus clock, turning off it will
introduce lockup issue during system suspend flow.  Let's mark
clk_gate_ufs_subsys as critical clock, thus keeps it on during
system suspend and resume.

Fixes: d374e6fd5088 ("clk: hisilicon: Add clock driver for hi3660 SoC")
Cc: stable@...r.kernel.org
Cc: Zhong Kaihua <zhongkaihua@...wei.com>
Cc: John Stultz <john.stultz@...aro.org>
Cc: Zhangfei Gao <zhangfei.gao@...aro.org>
Suggested-by: Dong Zhang <zhangdong46@...ilicon.com>
Signed-off-by: Leo Yan <leo.yan@...aro.org>
---
 drivers/clk/hisilicon/clk-hi3660.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/hisilicon/clk-hi3660.c b/drivers/clk/hisilicon/clk-hi3660.c
index f40419959656..794eeff0d5d2 100644
--- a/drivers/clk/hisilicon/clk-hi3660.c
+++ b/drivers/clk/hisilicon/clk-hi3660.c
@@ -163,8 +163,12 @@ static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = {
 	  "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
 	{ HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2",
 	  "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
+	/*
+	 * clk_gate_ufs_subsys is a system bus clock, mark it as critical
+	 * clock and keep it on for system suspend and resume.
+	 */
 	{ HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
-	  CLK_SET_RATE_PARENT, 0x50, 21, 0, },
+	  CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, },
 	{ HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
 	  CLK_SET_RATE_PARENT, 0x50, 28, 0, },
 	{ HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
-- 
2.17.1