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Message-ID: <CANLsYkzPV9t=wxOZjFDmxX+PUDhTo2i53cGrBBVUOmaVFijYsQ@mail.gmail.com>
Date: Wed, 20 Mar 2019 11:35:23 -0600
From: Mathieu Poirier <mathieu.poirier@...aro.org>
To: Wanglai Shi <shiwanglai@...ilicon.com>
Cc: "Suzuki K. Poulose" <suzuki.poulose@....com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
xuwei <xuwei5@...ilicon.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
devicetree@...r.kernel.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Leo Yan <leo.yan@...aro.org>,
Suzhuangluan <suzhuangluan@...ilicon.com>
Subject: Re: [PATCH v2 3/3] arm64: dts: hi3660: Add CoreSight support
On Wed, 20 Mar 2019 at 06:54, Wanglai Shi <shiwanglai@...ilicon.com> wrote:
>
> This patch adds DT bindings for the CoreSight trace components
> on hi3660, which is used by 96boards Hikey960.
>
> Signed-off-by: Wanglai Shi <shiwanglai@...ilicon.com>
This patch too needs to be on its own since it is maintained by Wei.
Thanks,
Mathieu
> ---
> .../boot/dts/hisilicon/hi3660-coresight.dtsi | 456 ++++++++++++++++++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 +
> 2 files changed, 458 insertions(+)
> create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> new file mode 100644
> index 000000000000..b6271fb407b7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi
> @@ -0,0 +1,456 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +/*
> + * dtsi for Hisilicon Hi3660 Coresight
> + *
> + * Copyright (C) 2016-2018 Hisilicon Ltd.
> + *
> + * Author: Wanglai Shi <shiwanglai@...ilicon.com>
> + *
> + */
> +/ {
> + soc {
> + /* A53 cluster internals */
> + etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecc40000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu0>;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecd40000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu1>;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xece40000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu2>;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xecf40000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu3>;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + funnel@...01000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0xec801000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + cluster0_funnel_out: endpoint {
> + remote-endpoint =
> + <&cluster0_etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster0_funnel_in0: endpoint {
> + remote-endpoint = <&etm0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + cluster0_funnel_in1: endpoint {
> + remote-endpoint = <&etm1_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + cluster0_funnel_in2: endpoint {
> + remote-endpoint = <&etm2_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + cluster0_funnel_in3: endpoint {
> + remote-endpoint = <&etm3_out>;
> + };
> + };
> + };
> + };
> +
> + etf@...02000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xec802000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + cluster0_etf_in: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + cluster0_etf_out: endpoint {
> + remote-endpoint =
> + <&combo_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + /* A73 cluster internals */
> + etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xed440000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu4>;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in0>;
> + };
> + };
> + };
> + };
> +
> + etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xed540000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu5>;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xed640000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu6>;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in2>;
> + };
> + };
> + };
> + };
> +
> + etm@...40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0xed740000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + cpu = <&cpu7>;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in3>;
> + };
> + };
> + };
> + };
> +
> + funnel@...01000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0xed001000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> + out-ports {
> + port {
> + cluster1_funnel_out: endpoint {
> + remote-endpoint =
> + <&cluster1_etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + cluster1_funnel_in0: endpoint {
> + remote-endpoint = <&etm4_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + cluster1_funnel_in1: endpoint {
> + remote-endpoint = <&etm5_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + cluster1_funnel_in2: endpoint {
> + remote-endpoint = <&etm6_out>;
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + cluster1_funnel_in3: endpoint {
> + remote-endpoint = <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + etf@...02000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xed002000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + cluster1_etf_in: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + cluster1_etf_out: endpoint {
> + remote-endpoint =
> + <&combo_funnel_in1>;
> + };
> + };
> + };
> + };
> +
> + /* An invisible combo funnel between clusters and top funnel */
> + funnel {
> + compatible = "arm,coresight-funnel";
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + combo_funnel_out: endpoint {
> + remote-endpoint =
> + <&top_funnel_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + combo_funnel_in0: endpoint {
> + remote-endpoint =
> + <&cluster0_etf_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + combo_funnel_in1: endpoint {
> + remote-endpoint =
> + <&cluster1_etf_out>;
> + };
> + };
> + };
> + };
> +
> + /* Top internals */
> + funnel@...31000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0xec031000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + top_funnel_out: endpoint {
> + remote-endpoint =
> + <&top_etf_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + top_funnel_in: endpoint {
> + remote-endpoint =
> + <&combo_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etf@...36000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xec036000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + top_etf_in: endpoint {
> + remote-endpoint =
> + <&top_funnel_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + top_etf_out: endpoint {
> + remote-endpoint =
> + <&replicator_in>;
> + };
> + };
> + };
> + };
> +
> + replicator {
> + compatible = "arm,coresight-replicator";
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint =
> + <&top_etf_out>;
> + };
> + };
> + };
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + replicator0_out0: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + replicator0_out1: endpoint {
> + remote-endpoint = <&tpiu_in>;
> + };
> + };
> + };
> + };
> +
> + etr@...33000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0xec033000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint =
> + <&replicator0_out0>;
> + };
> + };
> + };
> + };
> +
> + tpiu@...32000 {
> + compatible = "arm,coresight-tpiu", "arm,primecell";
> + reg = <0 0xec032000 0 0x1000>;
> + clocks = <&crg_ctrl HI3660_PCLK>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + port {
> + tpiu_in: endpoint {
> + remote-endpoint =
> + <&replicator0_out1>;
> + };
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> index 57ebefbd156f..36fdc9cd443d 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
> @@ -1216,3 +1216,5 @@
> };
> };
> };
> +
> +#include "hi3660-coresight.dtsi"
> --
> 2.17.1
>
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