linux-kernel - Re: [PATCH] clk: imx6q: Do not reparent unregistered IMX6QDL_CLK

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Message-ID: <20190321163511.qa267pvzgt3n57rn@fsr-ub1664-175>
Date:   Thu, 21 Mar 2019 16:35:11 +0000
From:   Abel Vesa <abel.vesa@....com>
To:     Mike Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        Fabio Estevam <fabio.estevam@....com>
CC:     Aisheng Dong <aisheng.dong@....com>,
        dl-linux-imx <linux-imx@....com>,
        Anson Huang <anson.huang@....com>,
        Rob Herring <robh@...nel.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: imx6q: Do not reparent unregistered
 IMX6QDL_CLK_PERIPH2

On 19-03-20 17:12:49, Abel Vesa wrote:
> The clock is registered later then these two re-parentings
> 

Ignore this patch. I'll send a patchset which has another fix for
another case like this one (plus the fix for the typo).

The patchset is actually switching all the imx6 and imx7 clocks
to clk_hw based API, but will include all the necessary fixes
for that to work.

> Signed-off-by: Abel Vesa <abel.vesa@....com>
> ---
>  drivers/clk/imx/clk-imx6q.c | 8 --------
>  1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
> index 708e7c5..c7b671e 100644
> --- a/drivers/clk/imx/clk-imx6q.c
> +++ b/drivers/clk/imx/clk-imx6q.c
> @@ -291,12 +291,6 @@ static void mmdc_ch1_disable(void __iomem *ccm_base)
>  	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL],
>  		       clk[IMX6QDL_CLK_PLL3_USB_OTG]);
>  
> -	/*
> -	 * Handshake with mmdc_ch1 module must be masked when changing
> -	 * periph2_clk_sel.
> -	 */
> -	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_CLK2]);
> -
>  	/* Disable pll3_sw_clk by selecting the bypass clock source */
>  	reg = readl_relaxed(ccm_base + CCM_CCSR);
>  	reg |= CCSR_PLL3_SW_CLK_SEL;
> @@ -311,8 +305,6 @@ static void mmdc_ch1_reenable(void __iomem *ccm_base)
>  	reg = readl_relaxed(ccm_base + CCM_CCSR);
>  	reg &= ~CCSR_PLL3_SW_CLK_SEL;
>  	writel_relaxed(reg, ccm_base + CCM_CCSR);
> -
> -	clk_set_parent(clk[IMX6QDL_CLK_PERIPH2], clk[IMX6QDL_CLK_PERIPH2_PRE]);
>  }
>  
>  /*
> -- 
> 2.7.4
>