lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Fri, 22 Mar 2019 06:06:18 -0700 From: Guenter Roeck <linux@...ck-us.net> To: "Ji-Ze Hong (Peter Hong)" <hpeter@...il.com>, wim@...ux-watchdog.orgw Cc: linux-watchdog@...r.kernel.org, linux-kernel@...r.kernel.org, stable@...r.kernel.org, "Ji-Ze Hong (Peter Hong)" <hpeter+linux_kernel@...il.com> Subject: Re: [PATCH V1 1/1] watchdog: f71808e_wdt: fix F81866 bit operation On 3/21/19 8:36 PM, Ji-Ze Hong (Peter Hong) wrote: > Fix error bit operation in watchdog_start() > Hmm ... does that mean it never worked ? Did you test it this time ? A secondary concern is that the watchdog doesn't _have_ to trigger WDTRST, but may also trigger PWOK. But that may be a separate issue. Please add: Fixes: 14b24a88a3660 ("watchdog: f71808e_wdt: Add F81866 support") > Signed-off-by: Ji-Ze Hong (Peter Hong) <hpeter+linux_kernel@...il.com> > --- > drivers/watchdog/f71808e_wdt.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) > > diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c > index 9a1c761258ce..9129485732c7 100644 > --- a/drivers/watchdog/f71808e_wdt.c > +++ b/drivers/watchdog/f71808e_wdt.c > @@ -387,18 +387,17 @@ static int watchdog_start(void) > > case f81866: > /* Set pin 70 to WDTRST# */ > - superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, > - BIT(3) | BIT(0)); > - superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, > - BIT(2)); > + superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, 3); > + superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, 0); > + superio_set_bit(watchdog.sioaddr, SIO_F81866_REG_PORT_SEL, 2); Better use superio_inb()/superio_outb(). The above is (much) more expensive, and we have no real idea what the impact of changing one bit at a time may be. Thanks, Guenter > + > /* > * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0. > * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch: > * BIT5: 0 -> WDTRST# > * 1 -> GPIO15 > */ > - superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, > - BIT(5)); > + superio_clear_bit(watchdog.sioaddr, SIO_F81866_REG_GPIO1, 5); > break; > > default: >
Powered by blists - more mailing lists