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Date: Fri, 22 Mar 2019 09:37:11 -0700 From: kan.liang@...ux.intel.com To: peterz@...radead.org, acme@...nel.org, mingo@...hat.com, linux-kernel@...r.kernel.org Cc: tglx@...utronix.de, jolsa@...nel.org, eranian@...gle.com, alexander.shishkin@...ux.intel.com, ak@...ux.intel.com, Kan Liang <kan.liang@...ux.intel.com> Subject: [PATCH V3 16/23] perf/x86/intel: Set correct weight for topdown subevent counters From: Andi Kleen <ak@...ux.intel.com> The top down sub event counters are mapped to a fixed counter, but should have the normal weight for the scheduler. So special case this. Signed-off-by: Andi Kleen <ak@...ux.intel.com> Signed-off-by: Kan Liang <kan.liang@...ux.intel.com> --- No changes since V2. arch/x86/events/intel/core.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 6a8a221dc188..31e4e283e7c5 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -5081,6 +5081,15 @@ __init int intel_pmu_init(void) * counter, so do not extend mask to generic counters */ for_each_event_constraint(c, x86_pmu.event_constraints) { + /* + * Don't limit the event mask for topdown sub event + * counters. + */ + if (x86_pmu.num_counters_fixed >= 3 && + c->idxmsk64 & INTEL_PMC_MSK_ANY_SLOTS) { + c->weight = hweight64(c->idxmsk64); + continue; + } if (c->cmask == FIXED_EVENT_FLAGS && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) { c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; -- 2.17.1
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