lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 22 Mar 2019 22:25:57 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Aaro Koskinen <aaro.koskinen@....fi>
Cc:     Vinod Koul <vkoul@...nel.org>,
        "David S. Miller" <davem@...emloft.net>, netdev@...r.kernel.org,
        linux-mips@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [BISECTED, REGRESSION] Broken networking on MIPS/OCTEON
 EdgeRouter Lite

> The OCTEON HW code knows only about RGMII. And looking at
> octeon ethernet staging driver it does phy connect always with
> PHY_INTERFACE_MODE_GMII. I did some experimentation, and it seems that
> with PHY_INTERFACE_MODE_RGMII_RXID it starts to work.. In the DT we have
> for ethernet for this board:
> 
> 	rx-delay = <0>;
> 	tx-delay = <0x10>;

These are not PHY properties. 

Looking at the code, it looks like these control delays the MAC
inserts. I don't see a binding document for these properties, so i've
no idea what 0x10 means. Before this driver moves out of staging,
these values should be changed to be in ns.

However, PHY_INTERFACE_MODE_RGMII_RXID would make sense if 0x10 is
sufficient to add the TX delay.

What the driver should however do is call of_of_get_phy_mode() to get
the phy-mode from the DT blob and pass that to of_phy_connect().

    Andrew

Powered by blists - more mailing lists