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Date:   Fri, 22 Mar 2019 10:58:03 +0200
From:   Roger Quadros <>
To:     <>
CC:     <>, <>,
        <>, Roger Quadros <>
Subject: [PATCH 0/4] phy: ti-pipe3: Match TRM sequence & settings

Hi Kishon,

We need to follow the TRM sequence and settings to ensure
that the DPLL & PHY operates correctly over the entire
temperature range.

Tested for SATA and USB. PCIe not tested.

Since this is a bug fix, please queue this for v5.1-rc. Thanks.


Roger Quadros (4):
  phy: ti-pipe3: Introduce mode property in driver data
  phy: ti-pipe3: improve DPLL stability for SATA & USB
  phy: ti-pipe3: Fix SATA & USB PHY power up sequence
  phy: ti-pipe3: Fix PCIe power up sequence

 drivers/phy/ti/phy-ti-pipe3.c | 362 +++++++++++++++++++++++++---------
 1 file changed, 265 insertions(+), 97 deletions(-)

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