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Message-Id: <20190323211612.860-13-fparent@baylibre.com>
Date: Sat, 23 Mar 2019 22:16:00 +0100
From: Fabien Parent <fparent@...libre.com>
To: matthias.bgg@...il.com, robh+dt@...nel.org, mark.rutland@....com
Cc: sean.wang@...nel.org, ryder.lee@...iatek.com,
hsin-hsiung.wang@...iatek.com, wenzhen.yu@...iatek.com,
chaotian.jing@...iatek.com, yong.mao@...iatek.com,
jjian.zhou@...iatek.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-mmc@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-serial@...r.kernel.org,
linux-spi@...r.kernel.org, linux-watchdog@...r.kernel.org,
linux-clk@...r.kernel.org, stephane.leprovost@...iatek.com,
Fabien Parent <fparent@...libre.com>
Subject: [PATCH 12/24] dt-bindings: mediatek: infracfg: add support for MT8516
Add binding documentation of infracfg for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@...libre.com>
---
.../bindings/arm/mediatek/mediatek,infracfg.txt | 1 +
include/dt-bindings/clock/mt8516-clk.h | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
index 417bd83d1378..cbc38a8ee985 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
@@ -15,6 +15,7 @@ Required Properties:
- "mediatek,mt7629-infracfg", "syscon"
- "mediatek,mt8135-infracfg", "syscon"
- "mediatek,mt8173-infracfg", "syscon"
+ - "mediatek,mt8516-infracfg", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
index 8d44cb32efba..956ee2c0748e 100644
--- a/include/dt-bindings/clock/mt8516-clk.h
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -8,6 +8,15 @@
#ifndef _DT_BINDINGS_CLK_MT8516_H
#define _DT_BINDINGS_CLK_MT8516_H
+/* INFRACFG */
+
+#define CLK_IFR_MUX1_SEL 0
+#define CLK_IFR_ETH_25M_SEL 1
+#define CLK_IFR_I2C0_SEL 2
+#define CLK_IFR_I2C1_SEL 3
+#define CLK_IFR_I2C2_SEL 4
+#define CLK_IFR_NR_CLK 5
+
/* TOPCKGEN */
#define CLK_TOP_CLK_NULL 0
--
2.20.1
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