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Message-Id: <20190323211612.860-14-fparent@baylibre.com>
Date: Sat, 23 Mar 2019 22:16:01 +0100
From: Fabien Parent <fparent@...libre.com>
To: matthias.bgg@...il.com, robh+dt@...nel.org, mark.rutland@....com
Cc: sean.wang@...nel.org, ryder.lee@...iatek.com,
hsin-hsiung.wang@...iatek.com, wenzhen.yu@...iatek.com,
chaotian.jing@...iatek.com, yong.mao@...iatek.com,
jjian.zhou@...iatek.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-mmc@...r.kernel.org,
linux-gpio@...r.kernel.org, linux-serial@...r.kernel.org,
linux-spi@...r.kernel.org, linux-watchdog@...r.kernel.org,
linux-clk@...r.kernel.org, stephane.leprovost@...iatek.com,
Fabien Parent <fparent@...libre.com>
Subject: [PATCH 13/24] dt-bindings: mediatek: apmixedsys: add support for MT8516
Add binding documentation of apmixedsys for MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@...libre.com>
---
.../bindings/arm/mediatek/mediatek,apmixedsys.txt | 1 +
include/dt-bindings/clock/mt8516-clk.h | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
index de4075413d91..c33d83f066c9 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt
@@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7629-apmixedsys"
- "mediatek,mt8135-apmixedsys"
- "mediatek,mt8173-apmixedsys"
+ - "mediatek,mt8516-apmixedsys"
- #clock-cells: Must be 1
The apmixedsys controller uses the common clk binding from
diff --git a/include/dt-bindings/clock/mt8516-clk.h b/include/dt-bindings/clock/mt8516-clk.h
index 956ee2c0748e..9cfca53cd78d 100644
--- a/include/dt-bindings/clock/mt8516-clk.h
+++ b/include/dt-bindings/clock/mt8516-clk.h
@@ -8,6 +8,16 @@
#ifndef _DT_BINDINGS_CLK_MT8516_H
#define _DT_BINDINGS_CLK_MT8516_H
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIVPLL 2
+#define CLK_APMIXED_MMPLL 3
+#define CLK_APMIXED_APLL1 4
+#define CLK_APMIXED_APLL2 5
+#define CLK_APMIXED_NR_CLK 6
+
/* INFRACFG */
#define CLK_IFR_MUX1_SEL 0
--
2.20.1
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