linux-kernel - [PATCH v1] arm64: dts: qcom: msm8998: Add PCIe PHY node

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Date:   Mon, 25 Mar 2019 18:37:31 +0100
From:   Marc Gonzalez <marc.w.gonzalez@...e.fr>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     Kishon Vijay Abraham <kishon@...com>,
        Jeffrey Hugo <jhugo@...eaurora.org>,
        MSM <linux-arm-msm@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>
Subject: [PATCH v1] arm64: dts: qcom: msm8998: Add PCIe PHY node

Add MSM8998 PCIe QMP PHY DT node.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@...e.fr>
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 39 +++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index f9a922fdae75..8344ed1bf08d 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -606,6 +606,45 @@
 			#thermal-sensor-cells = <1>;
 		};
 
+		phy@...6000 {
+			compatible = "qcom,msm8998-qmp-pcie-phy";
+			reg = <0x01c06000 0x18c>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			clock-names =
+				"aux",
+				"cfg_ahb",
+				"ref";
+			clocks =
+				<&gcc GCC_PCIE_PHY_AUX_CLK>,
+				<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+				<&gcc GCC_PCIE_CLKREF_CLK>;
+
+			reset-names =
+				"phy",
+				"common",
+				"cfg";
+			resets =
+				<&gcc GCC_PCIE_PHY_BCR>,
+				<&gcc GCC_PCIE_PHY_COM_BCR>,
+				<&gcc GCC_PCIE_PHY_NOCSR_COM_PHY_BCR>;
+
+			vdda-phy-supply = <&vreg_l1a_0p875>;
+			vdda-pll-supply = <&vreg_l2a_1p2>;
+
+			pciephy: lane@...6800 {
+				reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
+				#phy-cells = <0>;
+
+				clock-names = "pipe0";
+				clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+				clock-output-names = "pcie_0_pipe_clk_src";
+				#clock-cells = <0>;
+			};
+		};
+
 		tcsr_mutex_regs: syscon@...0000 {
 			compatible = "syscon";
 			reg = <0x1f40000 0x20000>;
-- 
2.17.1