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Message-ID: <20190326222441.GP18020@tassilo.jf.intel.com>
Date:   Tue, 26 Mar 2019 15:24:41 -0700
From:   Andi Kleen <ak@...ux.intel.com>
To:     kan.liang@...ux.intel.com
Cc:     peterz@...radead.org, acme@...nel.org, mingo@...hat.com,
        linux-kernel@...r.kernel.org, tglx@...utronix.de, jolsa@...nel.org,
        eranian@...gle.com, alexander.shishkin@...ux.intel.com
Subject: Re: [PATCH V4 04/23] perf/x86/intel: Support adaptive PEBSv4

> +	for (at = base; at < top; at += cpuc->pebs_record_size) {
> +		u64 pebs_status;
> +
> +		pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;
> +		pebs_status &= mask;
> +
> +		for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
> +			counts[bit]++;
> +	}

On Icelake pebs_status is always reliable, so I don't think we need
the two pass walking.

-Andi

> +
> +	for (bit = 0; bit < size; bit++) {
> +		if (counts[bit] == 0)
> +			continue;
> +
> +		event = cpuc->events[bit];
> +		if (WARN_ON_ONCE(!event))
> +			continue;
> +
> +		if (WARN_ON_ONCE(!event->attr.precise_ip))
> +			continue;
> +
> +		__intel_pmu_pebs_event(event, iregs, base,
> +				       top, bit, counts[bit],
> +				       setup_pebs_adaptive_sample_data);
> +	}
> +}

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