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Date:   Tue, 26 Mar 2019 15:30:16 +0900
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Atish Patra <atish.patra@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Anup Patel <anup@...infault.org>,
        Albert Ou <aou@...s.berkeley.edu>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        linux-riscv@...ts.infradead.org,
        Palmer Dabbelt <palmer@...ive.com>,
        Anup Patel <Anup.Patel@....com>,
        Damien Le Moal <Damien.LeMoal@....com>
Subject: [PATCH 5.0 29/52] clocksource/drivers/riscv: Fix clocksource mask

5.0-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Atish Patra <atish.patra@....com>

commit 32d0be018f6f5ee2d5d19c4795304613560814cf upstream.

For all riscv architectures (RV32, RV64 and RV128), the clocksource
is a 64 bit incrementing counter.

Fix the clock source mask accordingly.

Tested on both 64bit and 32 bit virt machine in QEMU.

Fixes: 62b019436814 ("clocksource: new RISC-V SBI timer driver")
Signed-off-by: Atish Patra <atish.patra@....com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Reviewed-by: Anup Patel <anup@...infault.org>
Cc: Albert Ou <aou@...s.berkeley.edu>
Cc: Daniel Lezcano <daniel.lezcano@...aro.org>
Cc: linux-riscv@...ts.infradead.org
Cc: Palmer Dabbelt <palmer@...ive.com>
Cc: Anup Patel <Anup.Patel@....com>
Cc: Damien Le Moal <Damien.LeMoal@....com>
Cc: stable@...r.kernel.org
Link: https://lkml.kernel.org/r/20190322215411.19362-1-atish.patra@wdc.com
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 drivers/clocksource/timer-riscv.c |    5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -58,7 +58,7 @@ static u64 riscv_sched_clock(void)
 static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = {
 	.name		= "riscv_clocksource",
 	.rating		= 300,
-	.mask		= CLOCKSOURCE_MASK(BITS_PER_LONG),
+	.mask		= CLOCKSOURCE_MASK(64),
 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 	.read		= riscv_clocksource_rdtime,
 };
@@ -103,8 +103,7 @@ static int __init riscv_timer_init_dt(st
 	cs = per_cpu_ptr(&riscv_clocksource, cpuid);
 	clocksource_register_hz(cs, riscv_timebase);
 
-	sched_clock_register(riscv_sched_clock,
-			BITS_PER_LONG, riscv_timebase);
+	sched_clock_register(riscv_sched_clock, 64, riscv_timebase);
 
 	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
 			 "clockevents/riscv/timer:starting",


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