linux-kernel - Re: [PATCH v2 1/2] arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 26 Mar 2019 18:33:21 +0800
From:   Seiya Wang <seiya.wang@...iatek.com>
To:     Stephen Boyd <sboyd@...nel.org>
CC:     Mark Rutland <mark.rutland@....com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Michael Turquette <mturquette@...libre.com>,
        "Rob Herring" <robh+dt@...nel.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] arm64: dts: mt8173: correct cpu type of cpu2 and
 cpu3 to cortex-a72

On Mon, 2019-02-25 at 14:51 +0800, Seiya Wang wrote:
> The cpu type of cpu2 and cpu3 should be cortex-a72, not cortex-a57.
> 
> Signed-off-by: Seiya Wang <seiya.wang@...iatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8173.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index 44374c506a1c..99675c51577a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -178,12 +178,12 @@
>  
>  		cpu2: cpu@100 {
>  			device_type = "cpu";
> -			compatible = "arm,cortex-a57";
> +			compatible = "arm,cortex-a72";
>  			reg = <0x100>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
>  			#cooling-cells = <2>;
> -			clocks = <&infracfg CLK_INFRA_CA57SEL>,
> +			clocks = <&infracfg CLK_INFRA_CA72SEL>,
>  				 <&apmixedsys CLK_APMIXED_MAINPLL>;
>  			clock-names = "cpu", "intermediate";
>  			operating-points-v2 = <&cluster1_opp>;
> @@ -191,12 +191,12 @@
>  
>  		cpu3: cpu@101 {
>  			device_type = "cpu";
> -			compatible = "arm,cortex-a57";
> +			compatible = "arm,cortex-a72";
>  			reg = <0x101>;
>  			enable-method = "psci";
>  			cpu-idle-states = <&CPU_SLEEP_0>;
>  			#cooling-cells = <2>;
> -			clocks = <&infracfg CLK_INFRA_CA57SEL>,
> +			clocks = <&infracfg CLK_INFRA_CA72SEL>,
>  				 <&apmixedsys CLK_APMIXED_MAINPLL>;
>  			clock-names = "cpu", "intermediate";
>  			operating-points-v2 = <&cluster1_opp>;

Since CLK_INFRA_CA72SEL has been added in mt8173-clk.h , please review
this patch. Thanks.