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Date:   Tue, 26 Mar 2019 08:20:16 -0500
From:   Rob Herring <robh@...nel.org>
To:     Guido Günther <agx@...xcpu.org>
Cc:     Maxime Ripard <maxime.ripard@...tlin.com>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        Robert Chiras <robert.chiras@....com>,
        Sam Ravnborg <sam@...nborg.org>,
        Fabio Estevam <festevam@...il.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v7 2/3] dt-bindings: phy: Add documentation for mixel dphy

On Mon, Mar 25, 2019 at 9:14 AM Guido Günther <agx@...xcpu.org> wrote:
>
> Add support for the MIXEL DPHY IP as found in the NXP's i.MX8MQ.

Please use get_maintainers.pl and send patches to the correct lists.

>
> Signed-off-by: Guido Günther <agx@...xcpu.org>
> Reviewed-by: Sam Ravnborg <sam@...nborg.org>
> ---
>  .../bindings/phy/mixel,mipi-dsi-phy.txt       | 29 +++++++++++++++++++
>  1 file changed, 29 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> new file mode 100644
> index 000000000000..d3646580412a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mixel,mipi-dsi-phy.txt
> @@ -0,0 +1,29 @@
> +Mixel DSI PHY for i.MX8
> +
> +The Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the
> +MIPI-DSI IP from Northwest Logic). It represents the physical layer for the
> +electrical signals for DSI.
> +
> +Required properties:
> +- compatible: Must be:
> +  - "mixel,imx8mq-mipi-dphy"
> +- clocks: Must contain an entry for each entry in clock-names.
> +- clock-names: Must contain the following entries:
> +  - "phy_ref": phandle and specifier referring to the DPHY ref clock
> +- reg: the register range of the PHY controller
> +- #phy-cells: number of cells in PHY, as defined in
> +  Documentation/devicetree/bindings/phy/phy-bindings.txt
> +  this must be <0>
> +
> +Optional properties:
> +- power-domains: phandle to power domain
> +
> +Example:
> +       mipi_dphy: mipi_dphy@...0030 {

dphy@...0030

> +               compatible = "mixel,imx8mq-mipi-dphy";
> +               clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
> +               clock-names = "phy_ref";
> +               reg = <0x30A00300 0x100>;
> +               power-domains = <&pd_mipi0>;
> +               #phy-cells = <0>;
> +        };
> --
> 2.20.1
>
> _______________________________________________
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> dri-devel@...ts.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

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