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Message-ID: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com>
Date: Tue, 26 Mar 2019 22:56:22 -0700
From: Sowjanya Komatineni <skomatineni@...dia.com>
To: <thierry.reding@...il.com>, <jonathanh@...dia.com>,
<talho@...dia.com>, <skomatineni@...dia.com>, <broonie@...nel.org>,
<robh+dt@...nel.org>, <mark.rutland@....com>,
<kyarlagadda@...dia.com>
CC: <ldewangan@...dia.com>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<devicetree@...r.kernel.org>
Subject: [PATCH V1 01/26] spi: tegra114: fix PIO transfer
Fixes: Use PIO bit in SPI_COMMAND1 register for PIO mode.
Current driver uses DMA_EN instead of PIO bit.
Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
---
drivers/spi/spi-tegra114.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index a76acedd7e2f..5a21bc808bb6 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -570,8 +570,9 @@ static int tegra_spi_start_cpu_based_transfer(
tspi->is_curr_dma_xfer = false;
- val |= SPI_DMA_EN;
- tegra_spi_writel(tspi, val, SPI_DMA_CTL);
+ val = tspi->command1_reg;
+ val |= SPI_PIO;
+ tegra_spi_writel(tspi, val, SPI_COMMAND1);
return 0;
}
--
2.7.4
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