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Message-ID: <20190327091929.73162-1-wangyan.wang@mediatek.com>
Date: Wed, 27 Mar 2019 17:19:23 +0800
From: wangyan wang <wangyan.wang@...iatek.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, CK Hu <ck.hu@...iatek.com>
CC: wangyan wang <wangyan.wang@...iatek.com>,
Matthias Brugger <matthias.bgg@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
chunhui dai <chunhui.dai@...iatek.com>,
Colin Ian King <colin.king@...onical.com>,
Sean Wang <sean.wang@...iatek.com>,
Ryder Lee <ryder.lee@...iatek.com>,
<linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<dri-devel@...ts.freedesktop.org>, <srv_heupstream@...iatek.com>
Subject: [PATCH V7 0/6] make mt7623 clock of hdmi stable
From: Wangyan Wang <wangyan.wang@...iatek.com>
V7 adopt maintainer's suggestion.
Here is the change list between V6 & V7
1. use readl directly & delete hdmi_phy->pll_rate in
mtk_hdmi_pll_recalc_rate().
in "drm/mediatek: recalculate hdmi ..."
2. detele mtk_hdmi_phy_read() in mtk_hdmi_phy.c.
in "fix the rate of parent for hdmi phy in MT2701"
3. optimize mtk_hdmi_pll_round_rate().
in "fix the rate of parent for hdmi phy in MT2701"
chunhui dai (6):
drm/mediatek: recalculate hdmi phy clock of MT2701 by querying
hardware
drm/mediatek: move the setting of fixed divider
drm/mediatek: using different flags of clk for HDMI phy
drm/mediatek: fix the rate and divder of hdmi phy for MT2701
drm/mediatek: using new factor for tvdpll in MT2701
drm/mediatek: fix the rate of parent for hdmi phy in MT2701
drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++---
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 35 +++---------------
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 6 +---
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 50 ++++++++++++++++++++++----
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 ++++++++++++
5 files changed, 76 insertions(+), 46 deletions(-)
--
2.14.1
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