linux-kernel - Re: [PATCH V4 4/5] mmc: mmci: stm32: define get_dctrl

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Date:   Wed, 27 Mar 2019 11:54:45 +0100
From:   Ulf Hansson <ulf.hansson@...aro.org>
To:     Ludovic Barre <ludovic.Barre@...com>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...com>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        DTML <devicetree@...r.kernel.org>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        linux-stm32@...md-mailman.stormreply.com
Subject: Re: [PATCH V4 4/5] mmc: mmci: stm32: define get_dctrl_cfg

On Wed, 27 Mar 2019 at 10:05, Ludovic Barre <ludovic.Barre@...com> wrote:
>
> From: Ludovic Barre <ludovic.barre@...com>
>
> This patch defines get_dctrl_cfg callback for sdmmc variant.
> sdmmc variant has specific stm32 transfer modes.
> sdmmc data transfer mode selection could be:
> -Block data transfer ending on block count.
> -SDIO multibyte data transfer.
> -MMC Stream data transfer (not used).
> -Block data transfer ending with STOP_TRANSMISSION command.
>
> Signed-off-by: Ludovic Barre <ludovic.barre@...com>
> ---
>  drivers/mmc/host/mmci.h             |  5 +++++
>  drivers/mmc/host/mmci_stm32_sdmmc.c | 18 ++++++++++++++++++
>  2 files changed, 23 insertions(+)
>
> diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
> index 35c91d0..82e9f94 100644
> --- a/drivers/mmc/host/mmci.h
> +++ b/drivers/mmc/host/mmci.h
> @@ -131,6 +131,11 @@
>  /* Control register extensions in the Qualcomm versions */
>  #define MCI_DPSM_QCOM_DATA_PEND        BIT(17)
>  #define MCI_DPSM_QCOM_RX_DATA_PEND BIT(20)
> +/* Control register extensions in STM32 versions */
> +#define MCI_DPSM_STM32_MODE_BLOCK      (0 << 2)
> +#define MCI_DPSM_STM32_MODE_SDIO       (1 << 2)
> +#define MCI_DPSM_STM32_MODE_STREAM     (2 << 2)
> +#define MCI_DPSM_STM32_MODE_BLOCK_STOP (3 << 2)
>
>  #define MMCIDATACNT            0x030
>  #define MMCISTATUS             0x034
> diff --git a/drivers/mmc/host/mmci_stm32_sdmmc.c b/drivers/mmc/host/mmci_stm32_sdmmc.c
> index cfbfc6f..8e83ae6 100644
> --- a/drivers/mmc/host/mmci_stm32_sdmmc.c
> +++ b/drivers/mmc/host/mmci_stm32_sdmmc.c
> @@ -265,10 +265,28 @@ static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
>         }
>  }
>
> +static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
> +{
> +       u32 datactrl;
> +
> +       datactrl = mmci_dctrl_blksz(host);
> +
> +       if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
> +           host->data->blocks == 1)
> +               datactrl |= MCI_DPSM_STM32_MODE_SDIO;
> +       else if (host->data->stop && !host->mrq->sbc)
> +               datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;

Just a question here. Does this mean that the controller sends the
stop command automatically when a transfer has finished successfully?

> +       else
> +               datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
> +
> +       return datactrl;
> +}
> +
>  static struct mmci_host_ops sdmmc_variant_ops = {
>         .validate_data = sdmmc_idma_validate_data,
>         .prep_data = sdmmc_idma_prep_data,
>         .unprep_data = sdmmc_idma_unprep_data,
> +       .get_datactrl_cfg = sdmmc_get_dctrl_cfg,
>         .dma_setup = sdmmc_idma_setup,
>         .dma_start = sdmmc_idma_start,
>         .dma_finalize = sdmmc_idma_finalize,
> --
> 2.7.4
>

Kind regards
Uffe