linux-kernel - [PATCH v2 01/13] arm64: dts: msm8998: thermal: split address space into two

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Message-Id: <e1f41103b412b6809fe43124256e4968c8fae9fd.1553853990.git.amit.kucheria@linaro.org>
Date:   Fri, 29 Mar 2019 15:42:07 +0530
From:   Amit Kucheria <amit.kucheria@...aro.org>
To:     linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        bjorn.andersson@...aro.org, edubezval@...il.com,
        andy.gross@...aro.org, David Brown <david.brown@...aro.org>
Cc:     devicetree@...r.kernel.org
Subject: [PATCH v2 01/13] arm64: dts: msm8998: thermal: split address space into two

We've earlier added support to split the register address space into TM
and SROT regions. Split up the regmap address space into two for msm8998
that has a similar register layout.

The order is important (TM before SROT) because we make an assumption
that SROT is always the second address space in order to support legacy
DTs.

Signed-off-by: Amit Kucheria <amit.kucheria@...aro.org>
---
 arch/arm64/boot/dts/qcom/msm8998.dtsi | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index 3fd0769fe648..ac25e9142cbd 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -590,17 +590,19 @@
 			cell-index = <0>;
 		};
 
-		tsens0: thermal@...a000 {
+		tsens0: thermal@...b000 {
 			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
-			reg = <0x10aa000 0x2000>;
+			reg = <0x10ab000 0x1000>, /* TM */
+			      <0x10aa000 0x1000>; /* SROT */
 
 			#qcom,sensors = <12>;
 			#thermal-sensor-cells = <1>;
 		};
 
-		tsens1: thermal@...d000 {
+		tsens1: thermal@...e000 {
 			compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
-			reg = <0x10ad000 0x2000>;
+			reg = <0x10ae000 0x1000>, /* TM */
+			      <0x10ad000 0x1000>; /* SROT */
 
 			#qcom,sensors = <8>;
 			#thermal-sensor-cells = <1>;
-- 
2.17.1