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Date: Fri, 29 Mar 2019 16:38:08 +0000 From: Lorenzo Pieralisi <lorenzo.pieralisi@....com> To: Marc Gonzalez <marc.w.gonzalez@...e.fr> Cc: Stanimir Varbanov <svarbanov@...sol.com>, Bjorn Helgaas <bhelgaas@...gle.com>, Srinivas Kandagatla <srinivas.kandagatla@...aro.org>, Andy Gross <andy.gross@...aro.org>, David Brown <david.brown@...aro.org>, Bjorn Andersson <bjorn.andersson@...aro.org>, PCI <linux-pci@...r.kernel.org>, MSM <linux-arm-msm@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>, Jeffrey Hugo <jhugo@...eaurora.org> Subject: Re: [PATCH v5] PCI: qcom: Use default config space read function On Mon, Mar 25, 2019 at 04:42:55PM +0100, Marc Gonzalez wrote: > Move the device class fudge to a proper fixup function, and remove > qcom_pcie_rd_own_conf() which has become useless. > > NB: dw_pcie_setup_rc() already did the right thing, but it's broken > on older qcom chips, such as 8064. > > Signed-off-by: Marc Gonzalez <marc.w.gonzalez@...e.fr> > --- > Changes from v4 to v5: Apply fixup to all qcom chips, the same way it was before > (thus the code remains functionally equivalent) > Drop Srinivas' Tested-by tag because of the change > --- > drivers/pci/controller/dwc/pcie-qcom.c | 23 ++++++----------------- > 1 file changed, 6 insertions(+), 17 deletions(-) Applied to pci/dwc for v5.2, thanks. Lorenzo > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index a7f703556790..0ed235d560e3 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -1129,25 +1129,8 @@ static int qcom_pcie_host_init(struct pcie_port *pp) > return ret; > } > > -static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, > - u32 *val) > -{ > - struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > - > - /* the device class is not reported correctly from the register */ > - if (where == PCI_CLASS_REVISION && size == 4) { > - *val = readl(pci->dbi_base + PCI_CLASS_REVISION); > - *val &= 0xff; /* keep revision id */ > - *val |= PCI_CLASS_BRIDGE_PCI << 16; > - return PCIBIOS_SUCCESSFUL; > - } > - > - return dw_pcie_read(pci->dbi_base + where, size, val); > -} > - > static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { > .host_init = qcom_pcie_host_init, > - .rd_own_conf = qcom_pcie_rd_own_conf, > }; > > /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ > @@ -1309,6 +1292,12 @@ static const struct of_device_id qcom_pcie_match[] = { > { } > }; > > +static void qcom_fixup_class(struct pci_dev *dev) > +{ > + dev->class = PCI_CLASS_BRIDGE_PCI << 8; > +} > +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, PCI_ANY_ID, qcom_fixup_class); > + > static struct platform_driver qcom_pcie_driver = { > .probe = qcom_pcie_probe, > .driver = { > -- > 2.17.1
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