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Date:   Sun, 31 Mar 2019 11:20:47 +0000
From:   Aisheng Dong <aisheng.dong@....com>
To:     Daniel Baluta <daniel.baluta@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>
CC:     "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "festevam@...il.com" <festevam@...il.com>,
        dl-linux-imx <linux-imx@....com>, Peng Fan <peng.fan@....com>,
        Anson Huang <anson.huang@....com>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "S.j. Wang" <shengjiu.wang@....com>, Teo Hall <teo.hall@....com>
Subject: RE: [PATCH] arm64: dts: imx8qxp: Add lpuart1/lpuart2/lpuart3 nodes

> From: Daniel Baluta
> Sent: Sunday, March 31, 2019 1:08 AM
> 
> lpuart nodes are part of the ADMA subsystem. See Audio DMA memory map in
> iMX8 QXP RM [1]
> 
> This patch is based on the dtsi file initially submitted by Teo Hall in i.MX NXP
> internal tree.
> 
> [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf
> 
> Signed-off-by: Teo Hall <teo.hall@....com>
> Signed-off-by: Daniel Baluta <daniel.baluta@....com>

Reviewed-by: Dong Aisheng <aisheng.dong@....com>

Regards
Dong Aisheng

> ---
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 33
> ++++++++++++++++++++++
>  1 file changed, 33 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> index 0cb939861a60..1adfe15c2ea5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -193,6 +193,39 @@
>  			status = "disabled";
>  		};
> 
> +		adma_lpuart1: serial@...70000 {
> +			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +			reg = <0x5a070000 0x1000>;
> +			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-parent = <&gic>;
> +			clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
> +			clock-names = "ipg";
> +			power-domains = <&pd IMX_SC_R_UART_1>;
> +			status = "disabled";
> +		};
> +
> +		adma_lpuart2: serial@...80000 {
> +			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +			reg = <0x5a080000 0x1000>;
> +			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-parent = <&gic>;
> +			clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
> +			clock-names = "ipg";
> +			power-domains = <&pd IMX_SC_R_UART_2>;
> +			status = "disabled";
> +		}
> +
> +		adma_lpuart3: serial@...90000 {
> +			compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +			reg = <0x5a090000 0x1000>;
> +			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-parent = <&gic>;
> +			clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
> +			clock-names = "ipg";
> +			power-domains = <&pd IMX_SC_R_UART_3>;
> +			status = "disabled";
> +		}
> +
>  		adma_i2c0: i2c@...00000 {
>  			compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
>  			reg = <0x5a800000 0x4000>;
> --
> 2.17.1

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