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Message-ID: <20190403075419.h2vvfiyzvq6xa2zs@flea>
Date:   Wed, 3 Apr 2019 09:54:19 +0200
From:   Maxime Ripard <maxime.ripard@...tlin.com>
To:     Jernej Skrabec <jernej.skrabec@...l.net>
Cc:     wens@...e.org, mturquette@...libre.com, sboyd@...nel.org,
        linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] clk: sunxi-ng: h6: Preset hdmi-cec clock parent

On Tue, Apr 02, 2019 at 11:06:22PM +0200, Jernej Skrabec wrote:
> H6 manual and BSP clock driver both states that hdmi-cec clock has two
> possible parents, osc32k and pll-periph0-2x with 36621 predivider.
> Because pll-periph0-2x is always 1.2 GHz, both parents give same
> hdmi-cec rate - 32768 Hz, which is exactly the rate needed for HDMI CEC
> controller to operate correctly.
>
> However, for some reason, HDMI CEC controller doesn't work if default
> parent (osc32k) is used. BSP HDMI driver also always use pll-periph0-2x
> as hdmi-cec clock parent.
>
> In order to solve the issue, preset hdmi-cec clock parent to
> pll-periph0-2x.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@...l.net>

Applied, thanks!
Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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