linux-kernel - Re: No 8254 PIT & no HPET on new Intel N3350 platforms causes kernel panic during early boot

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <alpine.DEB.2.21.1904031359530.1967@nanos.tec.linutronix.de>
Date:   Wed, 3 Apr 2019 14:01:26 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Daniel Drake <drake@...lessm.com>
cc:     Linux Kernel <linux-kernel@...r.kernel.org>,
        Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
        Hans de Goede <hdegoede@...hat.com>,
        david.e.box@...ux.intel.com,
        Endless Linux Upstreaming Team <linux@...lessm.com>,
        "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>, x86@...nel.org
Subject: Re: No 8254 PIT & no HPET on new Intel N3350 platforms causes kernel
 panic during early boot

On Wed, 3 Apr 2019, Thomas Gleixner wrote:
> For newer CPUs we might assume that:
> 
>  1) The TSC and APIC timer are actually usable
> 
>  2) The frequencies can be retrieved from CPUID or MSRs
> 
> If #1 and #2 are reliable we can avoid the whole calibration and interrupt
> delivery mess.
> 
> That means we need the following decision logic:
> 
>   1) If HPET is available in ACPI, boot normal.
> 
>   2) If HPET is not available, verify that the PIT actually counts. If it
>      does, boot normal.
> 
>      If it does not either:
> 
>      2A) Verify that this is a PCH 300/C240 and fiddle with that ISST bit.
> 
>      	 But that means that we need to chase PCH ids forever...
> 
>      2B) Shrug and just avoid the whole PIT/HPET magic all over the place:
> 
>      	 - Avoid the interrupt delivery check in the IOAPIC code as it's
>            uninteresting in that case. Trivial to do.
> 	 
> 	 - Prevent the TSC calibration code from touching PIT/HPET. It
>            should do that already when the TSC frequency can be retrieved
>            via CPUID or MSR. Should work, emphasis on should ...
> 
>     	   See the mess in: native_calibrate_tsc() and the magic tables in
> 	   tsc_msr.c how well that stuff works.
> 
> 	   The cpu_khz_from_cpuid() case at seems to not have these
> 	   issues. Knock on wood!
> 
>          - Prevent the APIC calibration code from touching PIT/HPET. That's
>            only happening right now when the TSC frequency comes from
> 	   the MSRs. No idea why the CPUID method does not provide that.
> 
> 	   CPUID leaf 0x16 provides the bus frequency, so we can deduce the
> 	   APIC timer frequency from there and spare the whole APIC timer
> 	   calibration mess:
> 
>   	       ECX Bits 15 - 00: Bus (Reference) Frequency (in MHz).
> 
> 	   It's usually not required on these newer CPUs because they
> 	   support TSC deadline timer, but you can disable that on the
> 	   kernel command line and some implementations of that were
> 	   broken. With that we are back to square one.
> 
> 	   So we need to make sure that these things work under all
> 	   circumstances.
> 
>    Rafael?

And we have to think hard about how we are going to provide that for
backporting in a digestable form. People are supposed to run recent stable
kernels (I'm not talking about dead kernels ...).

Thanks,

	tglx