lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 4 Apr 2019 11:48:24 +0000
From:   Bharat Kumar Gogada <bharatku@...inx.com>
To:     "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>
CC:     "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v2] PCI: xilinx-nwl: Fix Multi MSI data programming

> On Mon, Apr 01, 2019 at 05:00:40PM +0000, Bharat Kumar Gogada wrote:
> > Hi All,
> >
> > Please let me know if anyone has any inputs on this.
> >
> > Regards,
> > Bharat
> > >
> > > The current Multi MSI data programming fails if multiple end points
> > > requesting MSI and multi MSI are connected with switch, i.e the
> > > current multi MSI data being given is not considering the number of
> > > vectors being requested in case of multi MSI.
> > > Due to this if multiple end points are connected and requesting MSI
> > > and multi MSI combination, the multi MSI data is ending up using
> > > wrong MSI data, which might be used by different device.
> > >
> > > Fix Multi MSI data programming with required alignment by using
> > > number of vectors being requested.
> 
> I still do not understand what you mean I am sorry. An example is worth
> two thousand words, I would start with that as it stands this commit log
> does not provide any information on what you are actually fixing.
>
Hi Lorenzo, Thanks for your time. 
Yes, will add an example to describe the problem.
 
Regards,
Bharat
> > > Fixes: ab597d35ef11 ("PCI: xilinx-nwl: Add support for Xilinx NWL
> > > PCIe Host
> > > Controller")
> > > Signed-off-by: Bharat Kumar Gogada
> <bharat.kumar.gogada@...inx.com>
> > > ---
> > > V2:
> > >  - Added more description of fix
> > > ---
> > >  drivers/pci/controller/pcie-xilinx-nwl.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c
> > > b/drivers/pci/controller/pcie-xilinx-nwl.c
> > > index 81538d7..36669c5 100644
> > > --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> > > +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> > > @@ -484,7 +484,7 @@ static int nwl_irq_domain_alloc(struct
> > > irq_domain *domain, unsigned int virq,
> > >
> > >  	mutex_lock(&msi->lock);
> > >  	bit = bitmap_find_next_zero_area(msi->bitmap, INT_PCI_MSI_NR, 0,
> > > -					 nr_irqs, 0);
> > > +					 nr_irqs, nr_irqs - 1);
> > >  	if (bit >= INT_PCI_MSI_NR) {
> > >  		mutex_unlock(&msi->lock);
> > >  		return -ENOSPC;
> > > --
> > > 2.7.4
> >

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ